公开(公告)号：US3564502A

公开(公告)日：1971-02-16

申请号：US3564502D

申请日：1968-01-15

Applicant: IBM

Inventor： BOEHNER WILLIAM E ,  MCGILVRAY BRUCE L

IPC: G06F3/06 ,  G06F11/14 ,  G06F11/30 ,  G06F13/00 ,  G06F11/06

CPC classification number: G06F11/141

Abstract: POSITION INFORMATION ABOUT AN INTERRUPTED I/O DEVICE COMMUNICATED TO THE CPU AS A RESULT OF AN ERROR IN ITS CHANNEL, EVEN THROUGH NO ERROR OCCURRED IN THE I/O DEVICE. THE POSITIONAL INFORMATION ABOUT SHC I/O DEVICE IS CHOSEN IN RELATION TO THE EXECUTION STEPS IN A CHANNEL INSTRUCTION, SO THAT A RETRY MAY BE MADE OF THE CHANNEL INSTRUCTION BEING EXECUTED AT THE TIME OF THE CHANNEL ERROR. THE RECOVERY ACTION TO BE TAKEN AT THE I/O DEVICE FOR THE SAME CHANNEL INSTRUCTION VARIES WITH THE POSITIONAL INFORMATION EXISTING AT THE TIME OF THE CHANNEL ERROR. WITH START-STOP I/O DEVICES, THE INVENTION ENABLES A RETRY OF A SINGLE ERRONEOUSLY EXECUTED CHANNEL COMMAND BOTH DURING A COMMAND CHAINING OPERATION, AS WELL AS DURING NON-CHAINED COMMAND OPERATIONS. THE CHANNEL-I/O INTERFACE IS MONITORED BY A TIMEPOSITION SIGNALING CIRCUIT, WHICH DISCRETELY CYCLES AT DIFFERENT POINTS IN THE EXECUTION OF A CHANNEL INSTRUCTION (OR COMMAND) TO AN I/O DEVICE TO GENERATE CODES REPRESENTING RESPECTIVE TIME-POSITIONS DURING THE EXECUTION. AT THE MOMENT OF A CHANNEL ERROR, THE INPUT TO THE SIGNNALING CIRCUIT IS BLOCKED, SO THAT IT CONTINUES TO PROVIDE THE POSITION CODE EXISTING AT THE TIME OF THE CHANNEL ERROR. THE POSITION CODE IS TRANSMITTED INTO THE CHANNEL STATUS WORD OF A COMPUTER SYSTEM BY A CHANNEL INTERRUPT CAUSED BY THE CHANNEL ERROR. THEN, THE I/O MOVEMENT CONDITION EXISTING AT THE TIME OF THE ERROR IS OBTAINABLE FROM IN FORMATION IN THE CHANNEL STATUS WORD BY RELATING THE POSITION CODE TO THE PARTICULAR CHANNEL INSTRUCTION, SO THAT A RETRY OF THE CHANNEL INSTRUCTION CAN BE MADE.

公开(公告)号：US3533065A

公开(公告)日：1970-10-06

申请号：US3533065D

申请日：1968-01-15

Applicant: IBM

Inventor： MCGILVRAY BRUCE L ,  LANG DONALD J ,  BOEHNER WILLIAM E ,  BEE MARK W

IPC: G06F9/22 ,  G06F11/14 ,  G06F11/00

CPC classification number: G06F9/226 ,  G06F11/1407 ,  G06F11/141

公开(公告)号：US3928857A

公开(公告)日：1975-12-23

申请号：US39290073

申请日：1973-08-30

Applicant: IBM

Inventor： CARTER RICHARD S ,  HOGAN JR SPURGEON G ,  LEUNG WAN L ,  MCGILVRAY BRUCE L ,  WERNER ROBERT H

IPC: G06F9/38 ,  G06F9/06

CPC classification number: G06F9/381

Abstract: Apparatus for fetching instructions to an instruction register of a central processing unit, including instruction buffers for storing instructions prior to their execution in the CPU (lookahead) and apparatus for storing instructions which have been executed in the CPU (look-behind) in anticipation of their further use in, for example, programming loops. The look-behind apparatus comprises a multi-word buffer with its associated data register. The buffer data register, in addition to its function as part of the look-behind apparatus, also provides an additional level of look-ahead.

Abstract translation: 用于将指令读取到中央处理单元的指令寄存器的装置，包括用于在执行CPU之前存储指令的指令缓冲器（先行）以及用于存储在CPU（后视）中执行的指令的装置 预期他们在例如编程循环中进一步使用它们。 该查看装置包括具有相关联的数据寄存器的多字缓冲器。 缓冲器数据寄存器除了作为俯视设备的一部分的功能之外，还提供了一个额外的预览级别。

公开(公告)号：CA1176377A

公开(公告)日：1984-10-16

申请号：CA400593

申请日：1982-04-07

Applicant: IBM

Inventor： BULLIONS ROBERT J III ,  CURLEE THOMAS O III ,  GUM PETER H ,  MCGILVRAY BRUCE L ,  RICHARDSON ETHEL L

IPC: G06F9/44 ,  G06F9/455 ,  G06F9/46 ,  G06F12/10 ,  G11C9/00

Abstract: PO9-80-005 The described embodiment provides translation look-aside buffer (TLB) hardware in a CP that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment. Each TLB entry contains hardware which indicates whether the address sent by the CP Instruction Execution (IE) unit for translation is a guest or host/native request, and for a guest request if it is a real or virtual address. Intermediate translations for a double-level translation are inhibited from being loaded into the TLB. Guest entries are purged from the TLB without disturbing any host entries. An accelerated preferred guest mode in the CP forces its hardware adder translation hard ware to translate each accelerated preferred guest request, since it requires only a single level translation. A nonaccelerated guest request is instead translated by microcode. A limit check register is provided to check preferred guest addresses without causing performance degradation.

公开(公告)号：CA909954A

公开(公告)日：1972-09-12

申请号：CA909954D

Applicant: IBM

Inventor： MCGILVRAY BRUCE L ,  BOEHNER WILLIAM E

IPC: G06F11/14

公开(公告)号：CA989521A

公开(公告)日：1976-05-18

申请号：CA174806

申请日：1973-06-22

Applicant: IBM

Inventor： BURK JOHN L ,  HOGAN SPURGEON G JR ,  LARSON RUSSELL H ,  MCGILVRAY BRUCE L

IPC: G06F12/08 ,  G06F12/10

Abstract: This specification describes a virtual memory system comprising a main storage and a smaller high speed buffer. Both main storage and the buffer are real-address oriented. Current virtual-to-real address translations are retained in a Translation Look Aside Table (TLAT) and real addresses of data stored in the buffer are maintained in a buffer directory. The CPU-provided virtual address causes access to the TLAT and to the buffer directory. The virtual address stored in the word accessed from the TLAT is compared to the virtual address from the CPU and the real addresses accessed from the TLAT and the buffer directory are compared to each other. If both comparisons are equal, the data is accessed from the buffer.

公开(公告)号：CA1017871A

公开(公告)日：1977-09-20

申请号：CA206893

申请日：1974-08-13

Applicant: IBM

Inventor： CARTER RICHARD S ,  HOGAN SPURGEON G JR ,  LEUNG WAN L ,  MCGILVRAY BRUCE L ,  WERNER ROBERT H

IPC: G06F9/38

Abstract: Apparatus for fetching instructions to an instruction register of a central processing unit, including instruction buffers for storing instructions prior to their execution in the CPU (look-ahead) and apparatus for storing instructions which have been executed in the CPU (look-behind) in anticipation of their further use in, for example, programming loops. The look-behind apparatus comprises a multi-word buffer with its associated data register. The buffer data register, in addition to its function as part of the look-behind apparatus, also provides an additional level of look-ahead.

公开(公告)号：CA871359A

公开(公告)日：1971-05-18

申请号：CA871359D

Applicant: IBM

Inventor： BOEHNER WILLIAM E ,  BEE MARK W ,  MCGILVRAY BRUCE L ,  LANG DONALD J