公开(公告)号：JPS62103894A

公开(公告)日：1987-05-14

申请号：JP21990786

申请日：1986-09-19

Applicant: IBM

Inventor： JORDY GEORGE JOHN ,  MOONEY DONALD BLAISE ,  MOSLEY JOSEPH MICHAEL

IPC: G11C11/413 ,  G11C7/00 ,  G11C8/18 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56

公开(公告)号：DE3854012D1

公开(公告)日：1995-07-27

申请号：DE3854012

申请日：1988-02-24

Applicant: IBM

Inventor： MALEY GERALD ADRIAN ,  WEITZEL STEPHEN DOUGLAS ,  MOSLEY JOSEPH MICHAEL

IPC: H03K19/003 ,  H03K19/00 ,  H03K19/007

Abstract: A fault tolerant logic circuit capable of absorbing many D.C. and A.C. defects. The logic circuit employs a number of redundant logic gate circuits. The gate circuits are arranged in at least first and second interconnected signal paths. The logic gate circuits have two independent outputs. The two independent outputs are each connected to an input in a discrete one of the first and second interconnected signal paths.

公开(公告)号：DE3685717D1

公开(公告)日：1992-07-23

申请号：DE3685717

申请日：1986-10-10

Applicant: IBM

Inventor： JORDY GEORGE JOHN ,  MOONEY DONALD BLAISE ,  MOSLEY JOSEPH MICHAEL

IPC: G11C11/413 ,  G11C7/00 ,  G11C8/18 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56

公开(公告)号：DE3377850D1

公开(公告)日：1988-09-29

申请号：DE3377850

申请日：1983-06-16

Applicant: IBM

Inventor： DORLER JACK ARTHUR ,  MOSLEY JOSEPH MICHAEL ,  WEITZEL STEPHEN DOUGLAS

IPC: H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/06 ,  H03K17/16

公开(公告)号：DE3271766D1

公开(公告)日：1986-07-24

申请号：DE3271766

申请日：1982-07-13

Applicant: IBM

Inventor： DORLER JACK ARTHUR ,  MOSLEY JOSEPH MICHAEL ,  SEEGER RICHARD OWEN ,  WEITZEL STEPHEN DOUGLAS

IPC: H03F1/00 ,  H03K5/02 ,  H03K17/04 ,  H03K17/06 ,  H03K17/12 ,  H03K17/66 ,  H03K19/013 ,  H03K19/018 ,  H03K19/092

公开(公告)号：DE69022679T2

公开(公告)日：1996-05-02

申请号：DE69022679

申请日：1990-10-30

Applicant: IBM

Inventor： HAUSMAN KRISTEN ANN ,  GAUDENZI GENE JOSEPH ,  MOSLEY JOSEPH MICHAEL ,  TEMPEST SUSAN LYNN

IPC: H03K3/03 ,  H03K3/282

公开(公告)号：DE3784002T2

公开(公告)日：1993-08-19

申请号：DE3784002

申请日：1987-09-22

Applicant: IBM

Inventor： EVEN JOHN FARLEY ,  MOSLEY JOSEPH MICHAEL

IPC: H03K19/082 ,  H03K3/03 ,  H03K3/282 ,  H03L7/099 ,  H03L7/08

Abstract: A voltage controlled oscillator is formed of a plurality of cascaded inverter stages in a ring configuration. Each inverter stage is a grounded emitter circuit having an active pull-stage in order to achieve a short stage delay. The frequency of the ring oscillator is determined by the number of inverter stages, and the gain is selectable by coupling an external control voltage to only certain of the inverters. The VCO may be fabricated on a single integrated circuit along with the other circuits necessary to form a phase locked loop or other frequency generation system.

公开(公告)号：DE3268768D1

公开(公告)日：1986-03-13

申请号：DE3268768

申请日：1982-05-14

Applicant: IBM

Inventor： CHAN YUEN HUNG ,  DICKERSON JAMES EDWARD ,  KLARA WALTER STANLEY ,  KWAP THEODORE WILLIAM ,  MOSLEY JOSEPH MICHAEL

IPC: H03K5/12 ,  H03K17/04 ,  H03K19/013 ,  H03K19/086

公开(公告)号：DE3854012T2

公开(公告)日：1996-02-15

申请号：DE3854012

申请日：1988-02-24

Applicant: IBM

Inventor： MALEY GERALD ADRIAN ,  WEITZEL STEPHEN DOUGLAS ,  MOSLEY JOSEPH MICHAEL

IPC: H03K19/003 ,  H03K19/00 ,  H03K19/007

Abstract: A fault tolerant logic circuit capable of absorbing many D.C. and A.C. defects. The logic circuit employs a number of redundant logic gate circuits. The gate circuits are arranged in at least first and second interconnected signal paths. The logic gate circuits have two independent outputs. The two independent outputs are each connected to an input in a discrete one of the first and second interconnected signal paths.

公开(公告)号：DE68919376D1

公开(公告)日：1994-12-22

申请号：DE68919376

申请日：1989-02-28

Applicant: IBM

Inventor： MOSLEY JOSEPH MICHAEL ,  MULLGRAV ALLAN LESLIE JR ,  NOTO PHILIP KRANKIE ,  PETERSON CLARENCE IVAN ,  CULICAN EDWARD FRANCIS ,  DAVIS JOHN DONALD ,  EWEN JOHN FARLEY ,  MCCABE SCOTT ALLAN ,  PRITZLAFF PHILIPP EDWARD

IPC: H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H03K19/003 ,  H03L7/07 ,  H03L7/099 ,  H03L7/23 ,  H03L7/22 ,  H03L7/06

Abstract: A single logic gate array chip (1) is disclosed having a first portion (2) dedicated to the generation of one or more clock signals and the remaining portion (3) occupied by logic circuits. The first portion (2) uses the same gate array cell design as embodied in the logic circuits of the remaining portion (3). Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.