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公开(公告)号：GB2318936A
公开(公告)日：1998-05-06
申请号：GB9720705
申请日：1997-09-30
Applicant: IBM
Inventor： DREPS DANIEL MARK , MASLEID ROBERT P , MUHICH JOHN S
Abstract: A clock generation apparatus and method for generating clock signals for a microprocessor integrated circuit which includes a device which generates a reference frequency 26, an acoustic wave oscillator 18 having an oscillation frequency slightly faster than the reference frequency 26 and a circuit configuration coupled to the acoustic wave oscillator which generates frequency signals in response to an output of the acoustic wave oscillator. The frequency signals carry negligible jitter. The circuit configuration includes a quadrature rotator 12 for controlling clock phase, a clock distributor 14 for efficiently dispersing clock signals to the microprocessor integrated circuit, a bus divider 24 which provides a feedback clock signal phase aligned with the reference frequency, a phase detector 22 for detecting the phase difference of a bus clock signal and the feedback clock signal, and a digital filter 20 responsive to the phase detector.
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公开(公告)号：DE69322244T2
公开(公告)日：1999-07-01
申请号：DE69322244
申请日：1993-12-27
Applicant: IBM
Inventor： KAHLE JAMES A , MUHICH JOHN S , OEHLER RICHARD R , SILHA EDWARD J
IPC: G06F15/16 , G06F12/10 , G06F15/177 , G06F12/12
Abstract: A method and system for increasing memory concurrency in a multiprocessor computer system where each processor includs an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields. A reference bit is provided within a first individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been accessed for a read or write operation. A change bit is provided within a second individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been modified by a write operation. By storing the reference bit and change bit in separate individually accessible fields the reference bit and change bit may be concurrently updated by multiple processors.
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公开(公告)号：CA2229385A1
公开(公告)日：1998-09-24
申请号：CA2229385
申请日：1998-02-13
Applicant: IBM
Inventor： BUI CHI D , MUHICH JOHN S , CIRAULA MICHAEL K
Abstract: A method and device for selectively writing to portions of a memory word which i s cleared during the write operation. Information from all of the bytes in a memor y word are stored in a temporary space (a cache) prior to clearing the memory word, and the reafter, a portion of the stored information is written to at least one of the bytes in t he memory word, and new information is written to at least one other byte in the memory wo rd. The writing steps are accomplished using at least one multiplexer which selectively writes either stored information or new information in response to a control signal from the p rocessor. The temporary space (cache) includes a latch for each memory cell, and the multi plexer includes an enable line having on and off states, such that the multiplexer writ es information stored in a latch to the memory word if the enable line is in its of f state, but writes new information to the memory word if the enable line is in its on state. The memory word can be one of a plurality of memory words in the memory device (RAM), and t he memory word is accessed using an addressable word line.
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公开(公告)号：SG68025A1
公开(公告)日：1999-10-19
申请号：SG1998000432
申请日：1998-02-26
Applicant: IBM
Inventor： BUI CHI DUY , CIRAULA MICHAEL K , MUHICH JOHN S
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公开(公告)号：CA2254637A1
公开(公告)日：1999-07-07
申请号：CA2254637
申请日：1998-11-26
Applicant: IBM
Inventor： DREPS DANIEL M , MUHICH JOHN S , MASLEID ROBERT P
IPC: G06F1/06 , G06F1/04 , G06F1/10 , H03K5/135 , H03L7/06 , H03L7/081 , H03L7/099 , H03L7/08 , G06F1/12
Abstract: Among a plurality of signals, each phase-shifted with respect to the others, one signal is repeatedly substituted for another as a clock signal, to reduce a phase error of the clock signal with respect to a reference clock. The substitutions are timed to occur during intervals tending to reduce disturbances to the clock signal. Also, such substitution of a signal is responsive to occurrence of at least one cycle of the signal subsequent to the clock being supplied by an immediate predecessor of the signal, which tends to prevent erroneous substitutions of one signal for another.
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Patent Agency Ranking
公开(公告)号：CA2109043A1
公开(公告)日：1994-07-30
申请号：CA2109043
申请日：1993-10-22
Applicant: IBM
Inventor： MOORE CHARLES R , MUHICH JOHN S , REESE ROBERT J
Abstract: SYSTEM AND METHOD FOR TRANSFERRING INFORMATION BETWEEN MULTIPLE BUSES A method and system are provided for transferring information between multiple buses. Information is transferred through a first bus between multiple first bus devices. Information is transferred through a second bus between multiple second bus devices. Information is transferred through logic means between the first and second buses. Using the logic means, an action of a first bus device is enabled in response to a condition in which a second bus device waits for the action while the first bus device waits for a separate action on the second bus.
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公开(公告)号：CA2254637C
公开(公告)日：2003-07-22
申请号：CA2254637
申请日：1998-11-26
Applicant: IBM
Inventor： MASLEID ROBERT P , MUHICH JOHN S , DREPS DANIEL M
IPC: G06F1/06 , G06F1/04 , G06F1/10 , H03K5/135 , H03L7/06 , H03L7/081 , H03L7/099 , H03L7/08 , G06F1/12
Abstract: Among a plurality of signals, each phase-shifted with respect to the others, one signal is repeatedly substituted for another as a clock signal, to reduce a phase error of the clock signal with respect to a reference clock. The substitutions are timed to occur during intervals tending to reduce disturbances to the clock signal. Also, such substitution of a signal is responsive to occurrence of at least one cycle of the signal subsequent to the clock being supplied by an immediate predecessor of the signal, which tends to prevent erroneous substitutions of one signal for another.
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公开(公告)号：GB2318936B
公开(公告)日：2001-01-17
申请号：GB9720705
申请日：1997-09-30
Applicant: IBM
Inventor： DREPS DANIEL MARK , MASLEID ROBERT P , MUHICH JOHN S
Abstract: A clock generation apparatus and method for generating clock signals for a microprocessor integrated circuit. The clock generation apparatus includes a device which generates a reference frequency, an acoustic wave oscillator having an oscillation frequency slightly faster than the reference frequency and a circuit configuration coupled to the acoustic wave oscillator which generates frequency bearing signals in response to an output of the acoustic wave oscillator. The frequency bearing signals carry negligible jitter. The circuit configuration includes a quadrature rotator for controlling clock phase, a clock distributor for efficiently dispersing clock signals to the microprocessor integrated circuit, a bus divider which provides a feedback clock signal phase aligned with the reference frequency, a phase detector for detecting the phase difference of a bus clock signal and the feedback clock signal, and a digital filter responsive to the phase detector.
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公开(公告)号：CA2254651A1
公开(公告)日：1999-07-07
申请号：CA2254651
申请日：1998-11-26
Applicant: IBM
Inventor： MUHICH JOHN S , MASLEID ROBERT P , DREPS DANIEL M
Abstract: A method and apparatus are provided for generating synchronized clock signals. According to the method and apparatus, first and second pluralities of signals are generated, having time-varying phase differences with respect to a reference clock. The first clock is supplied by a succession of signals from among the first plurality of signals, in which one of the signals succeeds another responsive to a first phase difference. The second clock is supplied by a second succession of signals from among the second plurality of signals. One signal in the second succession of signals succeeds another responsive to a second phase difference. The succession among the first plurality of signals is also responsive to the second phase difference.
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公开(公告)号：DE69322244D1
公开(公告)日：1999-01-07
申请号：DE69322244
申请日：1993-12-27
Applicant: IBM
Inventor： KAHLE JAMES A , MUHICH JOHN S , OEHLER RICHARD R , SILHA EDWARD J
IPC: G06F15/16 , G06F12/10 , G06F15/177 , G06F12/12
Abstract: A method and system for increasing memory concurrency in a multiprocessor computer system where each processor includs an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields. A reference bit is provided within a first individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been accessed for a read or write operation. A change bit is provided within a second individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been modified by a write operation. By storing the reference bit and change bit in separate individually accessible fields the reference bit and change bit may be concurrently updated by multiple processors.
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