公开(公告)号：CA1248641A

公开(公告)日：1989-01-10

申请号：CA514222

申请日：1986-07-21

Applicant: IBM

Inventor： CHOW MELANIE M ,  CRONIN JOHN E ,  GUTHRIE WILLIAM L ,  KAANTA CARTER W ,  LUTHER BARBARA J ,  PATRICK WILLIAM J ,  PERRY KATHLEEN A ,  STANDLEY CHARLES L

IPC: H01L21/3205 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H05K3/04 ,  H05K3/10 ,  H05K3/46 ,  H01L21/72

Abstract: Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time. Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material. In those locations where the contact holes are exposed, the etching is continued into the first layer of insulation to uncover the underlying first level of patterned conductive material. The channels and via holes are overfilled with metallization. The excess metallization is removed by etching or by chem-mech (chemical-mechanical) polishing.

公开(公告)号：CA2011235A1

公开(公告)日：1990-11-15

申请号：CA2011235

申请日：1990-03-01

Applicant: IBM

Inventor： KU SAN-MEI ,  PERRY KATHLEEN A

IPC: H01L29/73 ,  H01L21/285 ,  H01L21/302 ,  H01L21/331 ,  H01L21/768 ,  H01L29/732

Abstract: A method of forming semiconductor device contacts includes the steps of: providing a semiconductor substrate (26) having at least two features e.g. a polysilicon land (36), another polysilicon land (48), and substrate (26),thereon whereat it is desired to make electrical connections; forming a layer (54) of etch stop material having a first etch characteristic over each of the features; forming a layer (56) of dielectric material having a second etch characteristic over each of the features; simultaneously etching at least two vias (58, 66, 60) through the layer of dielectric material using an etchant selective to the layer of dielectric material so as to substantially stop on the layer of etch stop material, the at least two vias including a via over each of the features; and extending the vias through the layer of etch stop material so as to expose the features for subsequent electrical connections (76, 74, 78).

公开(公告)号：CA2011235C

公开(公告)日：1993-06-29

申请号：CA2011235

申请日：1990-03-01

Applicant: IBM

Inventor： KU SAN-MEI ,  PERRY KATHLEEN A

IPC: H01L29/73 ,  H01L21/285 ,  H01L21/302 ,  H01L21/331 ,  H01L21/768 ,  H01L29/732 ,  H01L21/44

Abstract: METHOD OF FORMING CONTACTS TO A SEMICONDUCTOR DEVICE of the Invention A method of forming semiconductor device contacts includes the steps of: providing a semiconductor substrate having at least two features thereon whereat it is desired to make electrical connections; forming a layer of etch stop material having a first etch characteristic over each of the features; forming a layer of dielectric material having a second etch characteristic over each of the features; simultaneously etching at least two vias through the layer of dielectric material using an etchant selective to the layer of dielectric material so as to substantially stop on the layer of etch stop material, the at least two vias including a via over each of the features; and extending the vias through the layer of etch stop material so as to expose the features for subsequent electrical connections.

公开(公告)号：CA1245517A

公开(公告)日：1988-11-29

申请号：CA509373

申请日：1986-05-16

Applicant: IBM

Inventor： BEYER KLAUS D ,  GUTHRIE WILLIAM L ,  MAKAREWICZ STANLEY R ,  MENDEL ERIC ,  PATRICK WILLIAM J ,  PERRY KATHLEEN A ,  PLISKIN WILLIAM A ,  RISEMAN JACOB ,  SCHAIBLE PAUL M ,  STANDLEY CHARLES L

IPC: H01L21/3205 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/306

Abstract: A method is disclosed for producing coplanar metal/insulator films on a substrate according to a chem-mech polishing technique. In one example, a substrate having a patterned insulating layer of dielectric material thereon, is coated with a layer of metal. The substrate is then placed in a parallel polisher and the metal is removed elsewhere except in the holes where it is left intact. This is made possible through the use of an improved selective slurry which removes the metal much faster than the dielectric material. The insulating layer may then be used as an automatic etch stop barrier. In a second example a substrate having a paterned metallic layer is coated with an insulating layer and then subjected to chem-mech polishing. The structure is coplanarized by the chem-mech removal of the insulating material from the high points of the structure at a faster rate than from the lower points. Optional etch stop layers also may be used.