公开(公告)号：CA1273274A

公开(公告)日：1990-08-28

申请号：CA508583

申请日：1986-05-07

Applicant: IBM

Inventor： BEYER KLAUS D ,  MAKRIS JAMES S ,  MENDEL ERIC ,  NUMMY KAREN A ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/205

Abstract: A chemical-mechanical (chem-mech) method for removing SiO2 protuberances at the surface of a silicon chip, such protuberances including "bird heads". A thin etch stop layer of Si3N4 is deposited onto the wafer surface, which is then chem-mech polished with a SiO2 water based slurry. The Si3N4 acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si3N4 layer located on the top and at the sidewalls of the "bird' heads" and the underlying SiO2 protuberances are removed to provide a substantially planar integrated structure.

公开(公告)号：CA1090005A

公开(公告)日：1980-11-18

申请号：CA281576

申请日：1977-06-28

Applicant: IBM

Inventor： BEYER KLAUS D ,  DAS GOBINDA ,  POPONIAK MICHAEL R ,  YEH TSU-HSING

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/28 ,  H01L21/322 ,  H01L21/331 ,  H01L21/70

Abstract: SEMICONDUCTOR FABRICATION METHOD FOR IMPROVED DEVICE YIELD A method for fabricating bipolar semiconductor devices of large scale integration in which the formation of pipes, which result in shorts or leakages between two conductivity types of the semiconductor devices, is minimized. Prior to forming the emitters in the bipolar transistors, nucleation sites for crystallographic defects such as dislocation loops are formed in the base region near its surface. The emitters are then formed in base regions containing the nucleation sites and the sites are converted into electrically harmless dislocation loops during diffusion of the emitter impurity. Preferably, the nucleation sites are formed by implanting non-doping impurities, such as helium, neon, argon, krypton, xenon, silicon, and oxygen.

公开(公告)号：FR2357065A1

公开(公告)日：1978-01-27

申请号：FR7717613

申请日：1977-06-02

Applicant: IBM

Inventor： BEYER KLAUS D ,  DAS GOBINDA ,  POPONIAK MICHAEL R ,  YEH TSU-HSING

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/28 ,  H01L21/322 ,  H01L21/331

Abstract: A method for fabricating bipolar semiconductor devices of large scale integration in which the formation of pipes, which result in shorts or leakages between two conductivity types of the semiconductor devices, is minimized. Prior to forming the emitters in the bipolar transistors, nucleation sites for crystallographic defects such as dislocation loops are formed in the base region near its surface. The emitters are then formed in base regions containing the nucleation sites and the sites are converted into electrically harmless dislocation loops during diffusion of the emitter impurity. Preferably, the nucleation sites are formed by implanting non-doping impurities, such as helium, neon, argon, krypton, xenon, silicon, and oxygen.

公开(公告)号：CA1277778C

公开(公告)日：1990-12-11

申请号：CA580776

申请日：1988-10-20

Applicant: IBM

Inventor： BEYER KLAUS D ,  HSU LOUIS L ,  SCHEPIS DOMINIC J ,  SILVESTRI VICTOR J

IPC: H01L21/205 ,  H01L21/76 ,  H01L21/762 ,  H01L21/20

Abstract: DEFECT FREE EPITAXIALLY GROWN SILICON AND METHOD OF PRODUCING SAME A method for forming epitaxial grown silicon structure having substantially defect free outer surfaces and resulting structure is provided. A silicon substrate is provided, on which an epitaxial silicon crystal is grown. The outer surface layer of the silicon epitaxially grown silicon crystal will contain defective material which is removed by oxidation of the outer layer to silicon dioxide. This removes the defect containing outer layer, creating a new outer layer which is substantially defect free.

公开(公告)号：CA1245517A

公开(公告)日：1988-11-29

申请号：CA509373

申请日：1986-05-16

Applicant: IBM

Inventor： BEYER KLAUS D ,  GUTHRIE WILLIAM L ,  MAKAREWICZ STANLEY R ,  MENDEL ERIC ,  PATRICK WILLIAM J ,  PERRY KATHLEEN A ,  PLISKIN WILLIAM A ,  RISEMAN JACOB ,  SCHAIBLE PAUL M ,  STANDLEY CHARLES L

IPC: H01L21/3205 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/306

Abstract: A method is disclosed for producing coplanar metal/insulator films on a substrate according to a chem-mech polishing technique. In one example, a substrate having a patterned insulating layer of dielectric material thereon, is coated with a layer of metal. The substrate is then placed in a parallel polisher and the metal is removed elsewhere except in the holes where it is left intact. This is made possible through the use of an improved selective slurry which removes the metal much faster than the dielectric material. The insulating layer may then be used as an automatic etch stop barrier. In a second example a substrate having a paterned metallic layer is coated with an insulating layer and then subjected to chem-mech polishing. The structure is coplanarized by the chem-mech removal of the insulating material from the high points of the structure at a faster rate than from the lower points. Optional etch stop layers also may be used.