公开(公告)号：EP2047500A4

公开(公告)日：2009-08-26

申请号：EP07853503

申请日：2007-07-24

Applicant: IBM

Inventor： POGGE H BERNHARD ,  YU ROY R

IPC: H01L21/60 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L24/90 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/28 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01054 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1306 ,  H01L2924/15787 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2224/05552

公开(公告)号：EP1573799A4

公开(公告)日：2009-02-25

申请号：EP02808338

申请日：2002-12-20

Applicant: IBM

Inventor： POGGE H BERNHARD ,  YU ROY

IPC: H01L25/065 ,  H01L21/44 ,  H01L21/56 ,  H01L21/60 ,  H01L21/768 ,  H01L21/98 ,  H01L23/48 ,  H01L23/485

CPC classification number: H01L21/44 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A method is described for fabricating a three-dimensional integrated device including a plurality of vertically stacked and interconnected wafers. Wafers (1, 2, 3) are bonded together using bonding layers (26, 36) of thermoplastic material such as polyimide; electrical connections are realized by vias (12, 22) in the wafers connected to studs (27, 37). The studs connect to openings (13, 23) having a lateral dimension larger than that of the vias at the front surfaces of the wafers. Furthermore, the vias in the respective wafers need not extend vertically from the front surface to the back surface of the wafers. A conducting body (102), provided in the wafer beneath the device region and extending laterally, may connect the via with the matallized opening (103) in the back surface. Accordingly, the conducting path through the wafer may be led underneath the devices thereof. Additional connections may be made between openings (113) and studs (127) to form vertical heat conduction pathways between the wafers.

公开(公告)号：US3919060A

公开(公告)日：1975-11-11

申请号：US47932174

申请日：1974-06-14

Applicant: IBM

Inventor： POGGE H BERNHARD ,  POPONIAK MICHAEL R

IPC: H01L27/00 ,  C25F3/12 ,  H01L21/00 ,  H01L21/306 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  C25F3/00

CPC classification number: H01L21/76264 ,  C25F3/12 ,  H01L21/00 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02307 ,  H01L21/306 ,  H01L21/31662 ,  H01L21/7627 ,  H01L21/76281 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/117 ,  Y10S438/911

Abstract: A semiconductor fabrication method for producing dielectrically isolated silicon regions wherein high conductivity regions surrounding device regions to be electrically isolated are produced in a silicon body, the high conductivity regions anodically etched in a solution to selectively produce regions of porous silicon, the body exposed to an oxidizing environment while heated to an elevated temperature to oxidize the resultant porous silicon regions.

Abstract translation: 一种半导体制造方法，用于制造介电隔离的硅区域，其中在硅体中产生围绕要被电隔离的器件区域的高导电性区域，在溶液中阳极蚀刻的高导电性区域以选择性地产生多孔硅的区域， 氧化环境，同时加热到升高的温度以氧化所得的多孔硅区域。

公开(公告)号：US3669769A

公开(公告)日：1972-06-13

申请号：US3669769D

申请日：1970-09-29

Applicant: IBM

Inventor： BADAMI ANGELO V ,  EBERT EKKEHARD ,  KEMLAGE BERNARD M ,  KROELL KARL E ,  POGGE H BERNHARD

IPC: C30B25/02 ,  H01L21/205 ,  H01L21/22 ,  H01L7/36 ,  C23C13/00

CPC classification number: C30B29/06 ,  C30B25/02 ,  C30B29/08 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2205 ,  Y10S148/007 ,  Y10S148/037 ,  Y10S148/145 ,  Y10S438/916

Abstract: AUTODOPING IS MINIMIZED DURING THE GROWTH OF AN EPITAXIAL LAYER OF A SEMICONDUCTOR SUBSTRATE BY USING A GASEOUS REACTION MIXTURE THAT DEPOSITS THE INITIAL CAPPING LAYER AT A RELATIVELY SLOW DEPOSITION RATE. THE REACTION MIXTURE CONTAINS A RELATIVELY MINOR PORTION OF A SEMICONDUCTOR COMPOUND ALONG WITH THE CARRIER GAS. SUBSEQUENTLY, A SECOND GASEOUS REACTION MIXTURE CONTAINING A GREATER PORTION OF A COMPOUND OF A SEMICONDUCTOR MATERIAL IS USED TO COMPLETE THE DEPOSITION OF THE EPITXIAL LAYER. THIS IS DONE MERELY TO REDUCE THE TOTAL GROWTH CYCLE.

公开(公告)号：JP2006196885A

公开(公告)日：2006-07-27

申请号：JP2005364561

申请日：2005-12-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： POGGE H BERNHARD

IPC: H01L23/36 ,  H01L23/40

CPC classification number: H01L23/3735 ,  H01L23/3677 ,  H01L23/3738 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/00 ,  H01L2224/0401

Abstract: PROBLEM TO BE SOLVED: To provide a device and a structure for attaching a heat dissipation chip to a device chip so as to have a path of high thermal conductivity. SOLUTION: A structure and method are provided for dissipating heat from a semiconductor device chip. A first layer of a dielectric material (e.g. polyimide) is formed on a front side of a heat spreader (typically Si). A plurality of openings are formed through this first layer. The openings are filled with metal (typically Cu), thereby forming metal studs extending through the first layer. A second layer of metal is formed on the backside of the device chip. The first layer and the second layer are then bonded in a bonding process, thereby forming a bonding layer, where the metal studs contact the second layer. The bonding layer thus provides a thermal conductive path from the chip to the heat spreader. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于将散热芯片附接到器件芯片的器件和结构，以具有高导热性的路径。 解决方案：提供了用于从半导体器件芯片散热的结构和方法。 介电材料（例如聚酰亚胺）的第一层形成在散热器（通常为Si）的前侧。 通过该第一层形成多个开口。 开口用金属（通常为Cu）填充，从而形成延伸穿过第一层的金属螺柱。 第二层金属形成在器件芯片的背面。 然后在接合工艺中接合第一层和第二层，从而形成接合层，其中金属柱与第二层接触。 因此，接合层提供从芯片到散热器的导热路径。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2000299428A

公开(公告)日：2000-10-24

申请号：JP2000075124

申请日：2000-03-17

Applicant: IBM

Inventor： POGGE H BERNHARD

IPC: H01L25/18 ,  H01L21/68 ,  H01L23/538 ,  H01L23/544 ,  H01L25/04 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a module that has a chip mounted on a carrier board, with the use of a guide board which can be penetrated by ablation radiation. SOLUTION: A removable layer 37 is provided on a surface of a guide board 35. A first alignment guide 36 is formed on the removable layer, and a second alignment guide 21 is formed on the front side surface of a chip 30. By bringing the second alignment guide 21 into contact with the first alignment guide, the chip is aligned with the guide board. Then the chip 30 is mounted on the guide board 35. A carrier board 52 is mounted on a rear side surface of the chip. Then, using radiation which penetrates the guide board (generally laser radiation), an interface between the removable layer 37 and the guide board 35 is melted and removed, so that the guide board 35 is cut off. Then a thin film provided with metallic interconnection is provided on the front side surface of the chip.

公开(公告)号：CA1097826A

公开(公告)日：1981-03-17

申请号：CA305231

申请日：1978-06-12

Applicant: IBM

Inventor： BONDUR JAMES A ,  POGGE H BERNHARD

IPC: H01L21/76 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/762 ,  H01L27/00

Abstract: METHOD FOR FORMING ISOLATED REGIONS OF SILICON A method for isolating regions of silicon involving the formation of openings that have a suitable taper in a block of silicon, thermally oxidizing the surfaces of the openings, and filling the openings with a dielectric material to isolate regions of silicon within the silicon block. The method is particularly useful wherein the openings are made through a region of silicon having a layer of a high doping conductivity.

公开(公告)号：CA1108772A

公开(公告)日：1981-09-08

申请号：CA355850

申请日：1980-07-09

Applicant: IBM

Inventor： BONDUR JAMES A ,  POGGE H BERNHARD

IPC: H01L21/31

Abstract: METHOD FOR FORMING ISOLATED REGIONS OF SILICON A method for isolating regions of silicon involving the formation of openings that have a suitable taper in a block of silicon, thermally oxidizing the surfaces of the openings, and filling the openings with a dielectric material to isolate regions of silicon within the silicon block. The method is particularly useful wherein the openings are made through a region of silicon having a layer of a high doping conductivity.

公开(公告)号：AU2002368524A1

公开(公告)日：2004-07-22

申请号：AU2002368524

申请日：2002-12-20

Applicant: IBM

Inventor： POGGE H BERNHARD ,  YU ROY

IPC: H01L21/44 ,  H01L21/56 ,  H01L21/60 ,  H01L21/768 ,  H01L21/98 ,  H01L23/48 ,  H01L23/485 ,  H01L25/065 ,  H01L21/30 ,  H01L21/331 ,  H01L21/46 ,  H01L21/48 ,  H01L21/50

公开(公告)号：CA1092252A

公开(公告)日：1980-12-23

申请号：CA297585

申请日：1978-02-23

Applicant: IBM

Inventor： POGGE H BERNHARD

IPC: H01L27/00 ,  H01L21/306 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L27/04

Abstract: TOTAL DIELECTRIC ISOLATION A process which utilizes an anodized porous silicon technique to form dielectric isolation on one side of a semiconductor device is described. Regions of silicon semiconductor are fully isolated from one another by this technique. The starting water typically is predominently P with a P+ layer thereon. A P or N layer over the P+ layer is formed thereover such as by epitaxial growth. The surface of the silicon is oxidized and a photoresist layer applied thereto. Openings are formed in the photoresist. Openings are formed in the silicon dioxide using the photoresist as a mask and appropriate etching techniques. The openings in the silicon dioxide define the regions to be etched by reactive ion etching. Reactive ion etching is accomplished at least down to the P+ region. The structure is then subjected to the anodic etching technique which preferentially attacks the P+ layer to form porous silicon throughout the P+ layer. The structure is then placed in a thermal oxidation ambient until the porous silicon layer has been fully oxidized to silicon dioxide. The openings through the surface layer are filled up with oxide to fully isolate the P or N surface layer.