公开(公告)号：EP2377148A4

公开(公告)日：2016-03-16

申请号：EP09836605

申请日：2009-11-19

Applicant: IBM ,  FREESCALE SEMICONDUCTOR INC

Inventor： RAMACHANDRAN RAVIKUMAR ,  YAN HONGWEN ,  MOUMEN NAIM ,  SCHAEFFER JAMES KENYON ,  KRISHNAN SIDDARTH A ,  WONG KEITH KWONG HON ,  KWON UNOH ,  BELYANSKY MICHAEL P ,  WISE RICHARD

IPC: H01L21/3205 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/823857

公开(公告)号：EP2419925A4

公开(公告)日：2016-03-30

申请号：EP10765059

申请日：2010-04-14

Applicant: IBM

Inventor： CHUDZIK MICHAEL P ,  HENSON WILLIAM K ,  JHA RASHMI ,  LIANG YUE ,  RAMACHANDRAN RAVIKUMAR ,  WISE RICHARD S

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/49 ,  H01L29/7833

Abstract: The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.

公开(公告)号：JPH11102890A

公开(公告)日：1999-04-13

申请号：JP19685398

申请日：1998-07-13

Applicant: IBM ,  SIEMENS AG

Inventor： AKATSU HIROYUKI ,  HOYER RONALD ,  RAMACHANDRAN RAVIKUMAR

IPC: H01L21/304 ,  H01L21/306

Abstract: PROBLEM TO BE SOLVED: To prevent the formation of watermarks on a wafer after it has dried up by a method, wherein the wafer is rinsed by deionized water before it is dried up, then the wafer is rinsed by the first and the second organic solvents, and water is mixed into the solution. SOLUTION: When a silicon substrate is exposed to long-chain alcohol, for example, by conducting an exposing process wherein dipping, rinsing and spraying operations are performed, the density of water on the surface of the silicon substrate is reduced sharply. Then, the long-chain alcohol is removed by rinsing with other solution such as short-chain alcohol, for example. Higher class alcohol is dissolved by low class alcohol. Accordingly, higher class alcohol is removed from the surface of the silicon substrate when the silicon substrate is put in an isopropanol drier, for example. Then, water is removed from the surface of the substrate in a substrate drying process. The quantity of water remaining on the surface of the silicon substrate is reduced sharply by performing a process in which the substrate is dipped into alcohol. As a result, the formation of watermarks on wafer surface can be reduced sharply.

公开(公告)号：JPH11243085A

公开(公告)日：1999-09-07

申请号：JP32532998

申请日：1998-11-16

Applicant: IBM ,  SIEMENS AG

Inventor： RATH DAVID LEE ,  RAMACHANDRAN RAVIKUMAR

IPC: C09D9/00 ,  C09K13/08 ,  C11D3/39 ,  C11D7/08 ,  C11D11/00 ,  C23F1/16 ,  H01L21/302 ,  H01L21/304 ,  H01L21/308 ,  H01L21/311

Abstract: PROBLEM TO BE SOLVED: To effectively eliminate polymer and via residues from a substrate or a conductive material by setting etching agent composition to solution containing sulfuric acid of specific wt.%, hydrogen peroxide of specific wt.% or ozone of specific ppm, and hydrofluoric acid of specific ppm. SOLUTION: Etching agent composition is set to solution containing sulfuric acid of approximately 0.01-approximately 15 wt.%, hydrogen peroxide of approximately 0.01approximately 20 wt.%, hydrofluoric acid of approximately 0.1-approximately 100 ppm or ozone of approximately 1-approximately 30 ppm, and residues being substantially equal to water. The etching agent composition is made by mixing sulfuric acid solution such as solution of 98 wt.%, hydrogen peroxide solution such as solution of 30 wt.%, and hydrofluoric acid solution such as solution of 49 wt.% together, and by adding water where the sulfuric acid, hydrogen peroxide, and hydrofluoric acid of desired percents are given.

公开(公告)号：JPH11162913A

公开(公告)日：1999-06-18

申请号：JP27613498

申请日：1998-09-29

Applicant: SIEMENS AG ,  IBM

Inventor： AKATSU HIROYUKI ,  RAMACHANDRAN RAVIKUMAR

IPC: H01L21/304 ,  H01L21/00

Abstract: PROBLEM TO BE SOLVED: To clean and dry a semiconductor wafer by utilizing Marangoni effect, in which a liquid flow goes away from the wafer. SOLUTION: A housing 12, made up of upper and lower parts stores at least one wafer (W) during cleaning and drying. In a cleaning and drying apparatus, a movable supporting member 16 in the housing 12, a feeding means 40 for feeding organic vapor to the housing 12, and a feeding means 30 for feeding a wafer cleaning solution 60 to the housing 12 are provided. The wafer cleaning solution 60 is cooled sufficiently below an atmospheric temperature.

公开(公告)号：JP2000169831A

公开(公告)日：2000-06-20

申请号：JP26049599

申请日：1999-09-14

Applicant: SIEMENS AG ,  IBM

Inventor： LIN CHENTING ,  WANG JIUN-FANG ,  JAMIN FEN FEN ,  RAMACHANDRAN RAVIKUMAR

IPC: B24B37/00 ,  C09G1/02 ,  C09K3/14 ,  H01L21/302 ,  H01L21/304 ,  H01L21/321 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To obtain the subject composition capable of reducing the dishing on the surface of a wide patterned buried metal in a conductor, when an article having the patterned metal in the conductor is subjected to chemical and mechanical polishing treatments by adding a viscosity-increasing agent to a slurry containing a polishing agent in stead of a part of deionized water in the slurry. SOLUTION: A viscosity-improving agent is added in stead of a part of deionized water in a slurry containing a polishing material. The viscosity- improving agent is preferably glycerol and is replaced with 0.1-50 vol.% of the deionized water. The polishing material is preferably alumina. The composition preferably has a viscosity of 3.4-12 cps. When a conductor to be processed is treated, it is preferable that the surface of the conductor is exposed to the composition.

公开(公告)号：JPH11345805A

公开(公告)日：1999-12-14

申请号：JP10982099

申请日：1999-04-16

Applicant: SIEMENS AG ,  IBM

Inventor： RAMACHANDRAN RAVIKUMAR ,  NATZLE WESLEY ,  GUTSCHE MARTIN ,  AKATSU HIROYUKI ,  YU CHIEN

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/3065

Abstract: PROBLEM TO BE SOLVED: To avoid temporal coupling of reactive ion etching(RIE) and wet cleaning, and use of wet chemical cleaning, for anisotropic reactive ion etching processing, in RIE processing technique in which a via hole is formed so as to penetrate an intermediate dielectric layer(ILD). SOLUTION: In a method of removing a sidewall polymer rail from an Al/Cu metal wire on a semiconductor or a microelectronic composite structure by post-reactive ion etching, a mixture of an etching gas and an acid neutralizing gas is supplied into a vacuum chamber in which the composite structure is supported to form a water-soluble matter of the sidewall polymer rail left behind on the Al/Cu metal wire by RIE processing, removing the water-soluble matter with deionized water, and removing photoresist from the composite structure by a plasma processing only by means of water or a chemical down stream plasma etching.

公开(公告)号：JP2000311948A

公开(公告)日：2000-11-07

申请号：JP2000092149

申请日：2000-03-29

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ARNDT KENNETH C ,  BRINTZINGER AXEL C ,  CONTI RICHARD A ,  COTE DONNA R ,  NARAYAN CHANDRASEKHAR ,  RAMACHANDRAN RAVIKUMAR ,  RUPP THOMAS S ,  SENTEIRU K SURIINIVUASAN

IPC: H01L21/82 ,  H01H69/02 ,  H01H85/00 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure for generating a void fuse structure on a gate conductor stack. SOLUTION: A semiconductor substrate is provided, wherein a gate conductor stack 32 is provided on a shallow trench isolation region. Oxide layers 33 and 34 are formed on a substrate around the gate conductor stack 32, and an electric contact opening part etched to the substrate down to the oxide layer is filled with a first conductive material 40, establishing electric contact to the gate conductor stack. A conductive layer 41 of a second conductive material is allowed to stick to the oxide layer and the electric contact, and the oxide layer is anisotropically etched so that at least one etching hole, as far as the shallow trench isolation region through the oxide layer, is formed. A part 60 around the least the etching hole of the oxide layer is isotropically etched to form a void under at least a part of a conductive player pattern. The gate conductor stack comprises a fuse.

公开(公告)号：JP2000173920A

公开(公告)日：2000-06-23

申请号：JP34536299

申请日：1999-12-03

Applicant: SIEMENS AG ,  IBM

Inventor： RAMACHANDRAN RAVIKUMAR ,  NATZLE WESLEY ,  GUTSCHE MARTIN ,  AKATSU HIROYUKI ,  YU CHIEN

IPC: H01L21/302 ,  G03F7/42 ,  H01L21/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213

Abstract: PROBLEM TO BE SOLVED: To provide a method for removing post reactive ion etch sidewall polymer rails on an Al/Cu metal line of a semiconductor or microelectronic composite structure. SOLUTION: A mixture of an etching gas and an acid neutralizing gas is supplied to a vacuum chamger wherein a composite structure is supported to form a water soluble material of sidewall polymer rails left behind on an Al/Cu metal line from an anisotropic RIE(reactive ion etching) process. Then, the water soluble material is removed with deionized water and photo resist is removed from the composite structure by either a water-only plasma process or a chemical down stream etching method. Or, a water-only plasma process is formed to strip the photo resist layer of a semiconductor or microelectronic composite structure previously subjected to a RIE proccess. Then, a mixture of an etching gas and an acid neutralizing gas is supplied into a vacuum chamber on which the structure is supported to form a water soluble material of sidewall polymer rails and then the water soluble material is removed with deionized water.

公开(公告)号：WO2012106056A3

公开(公告)日：2012-10-18

申请号：PCT/US2012020020

申请日：2012-01-03

Applicant: IBM ,  RAMACHANDRAN RAVIKUMAR ,  DIVAKARUNI RAMACHANDRA ,  LI YING

Inventor： RAMACHANDRAN RAVIKUMAR ,  DIVAKARUNI RAMACHANDRA ,  LI YING

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336

CPC classification number: H01L29/401 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/49 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6656

Abstract: A semiconductor structure is provided that includes a semiconductor substrate 12 having a plurality of gate stacks 14' located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer 42, a work function metal layer 44 and a conductive metal 46. A spacer 22 is located on sidewalls of each gate stack and a self- aligned dielectric liner 30 is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner 30 is present on an upper surface of a semiconductor metal alloy 28. A contact metal 34 is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner 30. The structure also includes another contact metal 60 having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed.

Abstract translation: 提供半导体结构，其包括具有位于半导体衬底的表面上的多个栅极叠层14'的半导体衬底12。 每个栅极堆叠从底部到顶部包括高k栅极电介质层42，功函数金属层44和导电金属46.间隔物22位于每个栅极堆叠的侧壁上，并且自对准电介质衬垫30是 存在于每个间隔件的上表面上。 每个自对准电介质衬垫30的底表面存在于半导体金属合金28的上表面上。接触金属34位于相邻的栅极叠层之间并且通过自对准电介质衬垫30与每个栅极叠层分开。 该结构还包括另一接触金属60，其具有位于接触金属的上表面上并与其直接接触的部分以及位于栅叠层中的一个的导电金属上并与其直接接触的另一部分。 还公开了使用替代栅极和非替代栅极方案形成半导体结构的方法。