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    DUAL METAL AND DUAL DIELECTRIC INTEGRATION FOR METAL HIGH-K FETS
    1.
    发明公开
    DUAL METAL AND DUAL DIELECTRIC INTEGRATION FOR METAL HIGH-K FETS 审中-公开
    双金属和DOPPELDIELEKTRIK集成高k金属场效应管

    公开(公告)号：EP2419925A4

    公开(公告)日：2016-03-30

    申请号：EP10765059

    申请日：2010-04-14

    Applicant: IBM

    Inventor： CHUDZIK MICHAEL P ,  HENSON WILLIAM K ,  JHA RASHMI ,  LIANG YUE ,  RAMACHANDRAN RAVIKUMAR ,  WISE RICHARD S

    IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

    CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/49 ,  H01L29/7833

    Abstract: The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.

    METHOD FOR REDUCING FORMATION OF BLACK SILICON RELATED TO MANUFACTURE OF SEMICONDUCTOR DEVICE
    3.
    发明专利
    METHOD FOR REDUCING FORMATION OF BLACK SILICON RELATED TO MANUFACTURE OF SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPH11330419A

    公开(公告)日：1999-11-30

    申请号：JP6393599

    申请日：1999-03-10

    Applicant: SIEMENS AG ,  IBM

    Inventor： WANG TING-HAO ,  PERNG DUNG-CHING ,  DOBZINSKY DAVE M ,  WISE RICHARD S

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To reduce or prevent the formation of black silicon by conformally depositing a protective device layer on the surface of a wafer and by patterning the layer to remove the layer from a primary chip region, then depositing a pad stack and a hard mask on the wafer, and then subjecting them to DT etching. SOLUTION: A device layer 210 is formed on a wafer. The device layer 210 conformally covers a wafer surface, including the side and the bottom of the wafer. At least the edge and side of the wafer, where black silicon is produced, is protected, whereas a region 208 on which an IC is formed is not protected. A supporter 205 like a shadow ring is used to protect the edge of the wafer. The unprotected portion of the TEOS layer 210 in a primary chip region 208 is selectively removed from the wafer. A pad stack is formed, and then a hard mask layer 260 is deposited. The pad stack is patterned and then is subjected to a DT etching to form a DT.

    WIRING STRUCTURE FOR INTEGRATED CIRCUIT WITH REDUCED INTRALEVEL CAPACITANCE
    4.
    发明申请
    WIRING STRUCTURE FOR INTEGRATED CIRCUIT WITH REDUCED INTRALEVEL CAPACITANCE 审中-公开
    具有降低入侵电容的集成电路的接线结构

    公开(公告)号：WO2005104212A3

    公开(公告)日：2006-07-20

    申请号：PCT/US2005013601

    申请日：2005-04-21

    Applicant: IBM ,  WISE RICHARD S ,  CHEN BOMY A ,  HAKEY MARK C ,  YAN HONGWEN

    Inventor： WISE RICHARD S ,  CHEN BOMY A ,  HAKEY MARK C ,  YAN HONGWEN

    IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/53295 ,  H01L2221/1057 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features (16) in a layer of dielectric material (13), and forming spacers (20) on sidewalls (16s) of the features. Conductors (25) are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps (40) at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers (42, 12) above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors (25) has a bottom in contact with a low-k dielectric layer (12), a top in contact with another low-k dielectric (42), and sides in contact only with the air gaps (40). The air gaps serve to reduce the intralevel capacitance.

    Abstract translation: 形成用于集成电路的布线结构的方法包括以下步骤：在介电材料层（13）中形成多个特征（16），以及在特征的侧壁（16s）上形成间隔物（20）。 然后，导体（25）形成在特征中，通过间隔件与侧壁分离。 然后去除间隔物，在侧壁处形成气隙（40），使得导体通过气隙与侧壁分离。 在导体上方和下方的介电层（42,12）可以是介电常数小于导体之间的电介质的介电常数的低k电介质。 每个导体（25）的横截面具有与低k电介质层（12）接触的底部，与另一低k电介质（42）接触的顶部和仅与空气接触的侧面 间隙（40）。 气隙用于降低电容值。

    ANISOTROPIC ETCHING METHOD
    6.
    发明专利
    ANISOTROPIC ETCHING METHOD 失效

    公开(公告)号：JPH11260798A

    公开(公告)日：1999-09-24

    申请号：JP1536899

    申请日：1999-01-25

    Applicant: IBM

    Inventor： ARMACOST MICHAEL D ,  DOBUZINSKY DAVID M ,  MALINOWSKI JOHN C ,  NG HUNG Y ,  WISE RICHARD S ,  YU CHIENFAN

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311

    Abstract: PROBLEM TO BE SOLVED: To provide a method for anisotropic etching of a nitride layer on a substrate. SOLUTION: In this etching process, an etchant gas containing fluorohydrocarbon rich in hydrogen, oxidant and carbon source is used. It is preferable that the fluorohydrocarbon rich is hydrogen be CH3 or CH2 F2 , the carbon source be CO2 or CO, and the oxidant be O2 . It is preferable that the fluorohydrocarbon exsist in a gas of about 7-35 vol.%, the oxidant exsist in a gas of about 1-35 vol.%, and the carbon source exsists in a gas of about 30-92 vol.%.

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