公开(公告)号：CA1126629A

公开(公告)日：1982-06-29

申请号：CA348144

申请日：1980-03-21

Applicant: IBM

Inventor： ROTHMAN LAURA B ,  TOTTA PAUL A ,  WHITE JAMES F

IPC: H01L21/306 ,  H01L21/027 ,  H01L21/28 ,  H01L21/285 ,  H01L21/338 ,  H01L23/485 ,  H01L21/283

Abstract: A method for forming thin film patterns in the fabrication of integrated circuits utilizing a lift-off mask in an inverse vertical relationship with the desired metal film. The method involves the preliminary blanket deposition of the metal in-point, followed by a coating of a patterned lift-off mask over which is blanket coated a dryetch resistant material with subsequent removal of the lift-off mask, and dry etching of the exposed metal film. In one embodiment the dry-etch mask can comprise a diverse metal layer when a dry-etch ambient is employed which is passive to the d;verse metal. In another embodiment, where dry etch ambients are employed which are corrosive to the diverse metal which is desired in the final structure, it can be covered with a blanket layer of any convenient dry-etch resistant material, such as magnesium oxide, prior to removal of the lift-off mask. This method has effective application in the fabrication of Schottky barrier diodes, transistors, and other electronic components or discrete and integrated devices requiring high quality metal to semiconductor junctions or interfaces.

公开(公告)号：DE68922381T2

公开(公告)日：1995-11-23

申请号：DE68922381

申请日：1989-11-11

Applicant: IBM

Inventor： DEUTSCH ALINA ,  OPRYSKO MODEST M ,  RITSKO JOHN J ,  ROTHMAN LAURA B

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/544

Abstract: A thin film region 14 of a multichip carrier 10 is provided with at least one fabrication process or tooling monitor for monitoring the quality of the fabrication process during the sequential formation of the layers of the region 14. The process monitor is formed with a desired layer or layers of the thin film region, such as by a photolithographic process. A centrally disposed active wiring region 30 of a layer is surrounded by peripherally disposed fabrication monitor sites 32. The sites 32 can be located such that they do not occupy or interfere with the surface area required for the wiring region 30 while still being disposed near enough to the wiring region such that the electrical and physical characteristics of the thin film is substantially the same. Four different types of thin film fabrication process monitors are disclosed, including a line/via monitor, a dielectric monitor, a laser assisted repair monitor and a laser assisted engineering change monitor.

公开(公告)号：DE68922381D1

公开(公告)日：1995-06-01

申请号：DE68922381

申请日：1989-11-11

Applicant: IBM

Inventor： DEUTSCH ALINA ,  OPRYSKO MODEST M ,  RITSKO JOHN J ,  ROTHMAN LAURA B

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/544

Abstract: A thin film region 14 of a multichip carrier 10 is provided with at least one fabrication process or tooling monitor for monitoring the quality of the fabrication process during the sequential formation of the layers of the region 14. The process monitor is formed with a desired layer or layers of the thin film region, such as by a photolithographic process. A centrally disposed active wiring region 30 of a layer is surrounded by peripherally disposed fabrication monitor sites 32. The sites 32 can be located such that they do not occupy or interfere with the surface area required for the wiring region 30 while still being disposed near enough to the wiring region such that the electrical and physical characteristics of the thin film is substantially the same. Four different types of thin film fabrication process monitors are disclosed, including a line/via monitor, a dielectric monitor, a laser assisted repair monitor and a laser assisted engineering change monitor.

公开(公告)号：DE3277755D1

公开(公告)日：1988-01-07

申请号：DE3277755

申请日：1982-12-20

Applicant: IBM

Inventor： PLATTER VALERIA ,  ROTHMAN LAURA B ,  SCHAIBLE PAUL M ,  SCHWARTZ GERALDINE C

IPC: H01L21/3205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H05K3/46 ,  H01L21/90 ,  H01L23/52

Abstract: Coplanar conductor/insulator films with at least one level of metallization are produced by forming on a substrate a conductive pattern (5A, 6A) of a composite consisting of a lower layer (5A) of an aluminum based metal and an upper layer (6A) of hafnium with a coating (7A) of magnesium oxide covering its top surface, blanket depositing a layer of dielectic material whose thickness equals that of the conductive pattern, and wet etching said coating (7) of magnesium oxide for removal thereof together with the overlying portions of said dielectric coating thereon. … To produce structures with interconnected, coplanar conductor/insulator films on different levels the above process steps are repeated once or several times. … The hatnium layer is used to protect the aluminum based metal during the removal of the magnesium oxide, and as a registration enhancer for subsequent electron-beam processing.

公开(公告)号：CA1142272A

公开(公告)日：1983-03-01

申请号：CA356128

申请日：1980-07-14

Applicant: IBM

Inventor： LEVER REGINALD F ,  MAUER JOHN L IV ,  MICHEL ALWIN E ,  ROTHMAN LAURA B

IPC: H01L21/76 ,  H01L21/31 ,  H01L21/312 ,  H01L21/316 ,  H01L21/762 ,  H01L21/26

Abstract: A PLANAR DEEP OXIDE ISOLATION PROCESS A planar deep oxide isolation process for providing deep wide silicon dioxide filled trenches in a planar surface of a silicon semiconductor substrate is described. The process comprises the steps of forming deep wide trenches in a planar surface of the silicon substrate; forming a thin layer of silicon dioxide on the planar surface of the silicon substrate and the exposed silicon surfaces of the deep wide trenches; applying resin glass (polysiloxane) to the planar surface of the semiconductor substrate and within the deep wide trenches; spinning off at least a portion of the resin glass on the planar surface of the substrate; baking the substrate at a low temperature; exposing the resin glass contained within the deep wide trenches of the substrate to the energy of an E-beam; developing the resin glass contained on said substrate in a solvent; heating the substrate in oxygen to convert the resin glass contained within the deep wide trenches to silicon dioxide; depositing a layer of silicon dioxide to provide a planar silicon dioxide surface on the exposed surface of the substrate; and planarize exposed silicon dioxide surface to silicon of substrate. FI9-79-011