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    1.
    发明专利
    未知

    公开(公告)号：DE2430127A1

    公开(公告)日：1975-01-16

    申请号：DE2430127

    申请日：1974-06-22

    Applicant: IBM

    Inventor： BROWN PAUL JOSEPH ,  SMITH RONALD MORTON

    IPC: G06F12/14 ,  G06F9/46 ,  G06F9/52 ,  G06F12/00 ,  G06F15/16 ,  G06F15/177 ,  G06F9/18 ,  G06F13/06

    Abstract: 1432279 Data processing INTERNATIONAL BUSINESS MACHINES CORP 15 May 1974 [29 June 1973] 21509/74 Heading G4A In a multiprogrammed or multiprocessor system in which a plurality of users (programs or processors 12, 13) share storage 10, data which has been accessed by a user from a location 18 in shared storage is held in a register 22 and after processing by a program, the data originally accessed is compared with the data now in the accessed location 18 and, depending on the result of the comparison, the data in the accessed location 18 is replaced by the result 23 of processing the data or the data in the register 22 is replaced by the data from the accessed location 18. In this way, interlocks which are normally provided can be dispensed with as data which has been modified by an interrupting program, or by a processor of higher priority than the processor which initially accessed the data for processing, replaces the unmodified data so that processing may be repeated with the modified data. A comparator 25 detects whether or not the accessed data has been modified, this being in response to a special Compare & Swap instruction embedded in the program at at the end of a processing sequence, and if inequality (data modified) is found a condition code CC1 is set to cause a conditional branch back to the beginning of the processing sequence. In a multiprocessor system an interlock must be provided to prevent a processor 12 from accessing shared storage while another processor 13 is making the decision whether or not to replace the contents of a location 18 by modified data 23 which has just been generated therein.

    2.
    发明专利
    未知

    公开(公告)号：DE69129778T2

    公开(公告)日：1999-03-11

    申请号：DE69129778

    申请日：1991-07-31

    Applicant: IBM

    Inventor： GREEN LUCINA LI-NIEN ,  KELLY MICHAEL JAMES ,  SMITH RONALD MORTON ,  THOMAS JULIAN ,  YEH PHIL CHI-CHUNG

    IPC: G09C1/00 ,  G06F12/14 ,  H04L9/08

    Abstract: A facility for making dynamic changes to a system master key without stopping the system, and without loss of integrity to ongoing cryptographic operations. A version number is generated and associated with the current master key. A dynamic change is made to the master key, resulting in the then current master key becoming the old master key, and a "new" current master key (with a new version number) being placed into operation. Subsequent cryptographic requests using a supplied key enciphered under the old master key are identified by means of a supplied version number associated with the supplied key. This identification triggers a reencipher operation, reenciphering the supplied key under the now current master key - after which the cryptographic operation proceeds. Unique patterns are generated to verify the contents of the master key registers, and to authorize normal use of the cryptographic facility, and issuers of key-change operations.

    3.
    发明专利
    未知

    公开(公告)号：DE69129778D1

    公开(公告)日：1998-08-20

    申请号：DE69129778

    申请日：1991-07-31

    Applicant: IBM

    Inventor： GREEN LUCINA LI-NIEN ,  KELLY MICHAEL JAMES ,  SMITH RONALD MORTON ,  THOMAS JULIAN ,  YEH PHIL CHI-CHUNG

    IPC: G09C1/00 ,  G06F12/14 ,  H04L9/08

    Abstract: A facility for making dynamic changes to a system master key without stopping the system, and without loss of integrity to ongoing cryptographic operations. A version number is generated and associated with the current master key. A dynamic change is made to the master key, resulting in the then current master key becoming the old master key, and a "new" current master key (with a new version number) being placed into operation. Subsequent cryptographic requests using a supplied key enciphered under the old master key are identified by means of a supplied version number associated with the supplied key. This identification triggers a reencipher operation, reenciphering the supplied key under the now current master key - after which the cryptographic operation proceeds. Unique patterns are generated to verify the contents of the master key registers, and to authorize normal use of the cryptographic facility, and issuers of key-change operations.

    6.
    发明专利
    未知

    公开(公告)号：DE3685913T2

    公开(公告)日：1993-02-25

    申请号：DE3685913

    申请日：1986-04-21

    Applicant: IBM

    Inventor： BUCHHOLZ WERNER ,  SMITH RONALD MORTON ,  WEHRLY DAVID SILER

    IPC: G06F9/48 ,  G06F9/315 ,  G06F9/38 ,  G06F15/78 ,  G06F17/16 ,  G06F15/347 ,  G06F15/76

    Abstract: A vector processor is disclosed which processes vectors that can have more elements than a vector register can contain at one time. Vectors are processed in sections in which the section size is determined by the number of element locations in a vector register. A vector count register controls the number of elements processed by each vector instruction. A vector interruption index points to the first or next element in a vector to be processed by a vector instruction either when it is first issued or when it is re-issued following an interruption of the vector instruction. A general purpose (length) register contains the entire length of the vector to be 1 processed. A single instruction, which starts a vector sectioning loop, provides for the smaller of the section size or the content of the length register to be loaded into the vector count register. During the operation of the sectioning loop, the vector count register is repetitively subtracted from the content of the first general purpose register and the resulting residual vector length is placed back in the first general purpose register until all of the elements have been processed.

    9.
    发明专利
    未知

    公开(公告)号：DE3685913D1

    公开(公告)日：1992-08-13

    申请号：DE3685913

    申请日：1986-04-21

    Applicant: IBM

    Inventor： BUCHHOLZ WERNER ,  SMITH RONALD MORTON ,  WEHRLY DAVID SILER

    IPC: G06F9/48 ,  G06F9/315 ,  G06F9/38 ,  G06F15/78 ,  G06F17/16 ,  G06F15/347 ,  G06F15/76

    Abstract: A vector processor is disclosed which processes vectors that can have more elements than a vector register can contain at one time. Vectors are processed in sections in which the section size is determined by the number of element locations in a vector register. A vector count register controls the number of elements processed by each vector instruction. A vector interruption index points to the first or next element in a vector to be processed by a vector instruction either when it is first issued or when it is re-issued following an interruption of the vector instruction. A general purpose (length) register contains the entire length of the vector to be 1 processed. A single instruction, which starts a vector sectioning loop, provides for the smaller of the section size or the content of the length register to be loaded into the vector count register. During the operation of the sectioning loop, the vector count register is repetitively subtracted from the content of the first general purpose register and the resulting residual vector length is placed back in the first general purpose register until all of the elements have been processed.

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