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    1.
    发明专利
    未知

    公开(公告)号：DE69231611D1

    公开(公告)日：2001-02-01

    申请号：DE69231611

    申请日：1992-10-30

    Applicant: IBM

    Inventor： BAUM RICHARD IRWIN ,  PLAMBECK KENNETH ERNEST ,  SCALZI CASPER ANTHONY ,  SCHMALZ RICHARD JOHN ,  SINHA BHASKAR

    IPC: G06F12/10 ,  G06F12/02

    Abstract: A method and means of translating a large logical address as a large virtual address (LVA) when dynamic address translator (DAT) is on and for using the large logical address as a large real address (LRA) when DAT (33) is off. This LVA or LRA is used for locating data and instructions in a computer memory. Each LVA is separated into three concatenated parts: a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and a low-order DAT VA part having the same size as the conventional type of virtual address. The low-order DAT VA part is translated by the associated translation table (48). This address translation of the low-order (DAT VA) part provides a real address that represents the translation of the LVA. The LVAs map into a large virtual address space (LVAS) represented by the sequence of valid ALEs in the set of ALs respectively represented by the sequence of valid ADEs in the AD. The sequence of ADEs in the AD respectively locate the ALs containing the ALEs which represent the LVAS. Thus, the range of LVAs (starting from zero) in the LVAS maps to the respective ALEs in the set of ALs. Each AL may contain a respective offset of ALEs that are not part of the LVAS.

    2.
    发明专利
    未知

    公开(公告)号：AT146886T

    公开(公告)日：1997-01-15

    申请号：AT90115517

    申请日：1990-08-13

    Applicant: IBM

    Inventor： BLANDY GEOFFREY OWEN ,  EMMES DAVID BRUCE ,  HILL RONALD FRANKLIN ,  LINDQUIST DAVID BRUCE ,  PLAMBECK KENNETH ERNEST ,  SCALZI CASPER ANTHONY ,  SCHMALZ RICHARD JOHN

    IPC: G06F12/10 ,  G06F12/14

    Abstract: A single non-privileged instruction copies a page of data from a source virtual address to a destination virtual address, regardless of which of plural electronic storage media contain the page locations, and without the intervention of any supervisory program when media and virtual addressing have been previously determined for the locations of the subject pages. The instruction is not required to specify which of the plural media it will use, does not require its user to know what backing media it will access, does not require main storage (MS) to be one of its backing media, and allows different types of physical addressing to be used by the different backing media. The instruction can lock any page for use in an MP. No physical direction of data movement is provided within the non-privileged machine instruction, which only designates virtual direction of movement. The separation of virtual direction from physical direction is done by avoiding instruction control over selection of electronic media. The non-privileged instruction can nevertheless express a preference for obtaining a copy of the destination page in an electronic medium in which the content of the page can be processed by further instructions. Also, the instruction can cause invocation of a privileged control program to avoid the need for a following condition code test instruction. A privileged instruction is also provided to wait for the completion of the unprivileged instruction and to invalidate a non-main storage (MS) medium page whether it is unlocked or locked, either correctly or incorrectly.

    3.
    发明专利
    未知

    公开(公告)号：DE3850181D1

    公开(公告)日：1994-07-21

    申请号：DE3850181

    申请日：1988-07-05

    Applicant: IBM

    Inventor： BEAN GEORGE HENRY ,  BORDEN TERRY LEE ,  FARRELL MARK STEVEN ,  GUM PETER HERMON ,  HOUGH ROGER ELDRED ,  JOHNSON FRANCIS EDWARD ,  MCCAULEY DONALD WILLIAM ,  RAKHMILEVICH MARK EMMANUEL ,  RATHJEN JOHN CORD ,  SCALZI CASPER ANTHONY ,  SCANLON JOHN FENTON ,  WYMAN LESLIE WOOD

    IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50 ,  G06F12/10

    Abstract: The embodiment discloses a method and means for partitioning the resources in a data processing system into a plurality of logical partitions. Host control code may be embodied in programming, microcode, or by special hardware to enable highly efficient operation of a plurality of preferred guest programming systems in the different partitions of the system. The main storage, expanded storage, the channel, and subchannel resources of a system are assigned to the different logical partitions in the system to enable a plurality of preferred guest programming systems to run simultaneously in the different partitions. This invention automatically relocates the absolute addresses of the I/O channel and subchannel resources in the system to their assigned partitions. Also the absolute and virtual addresses of the different guest programming systems are relocated into, as well as page addresses for any expanded storage, their assigned partitions. The guest programming systems generally will be different operating systems. The logical CPU(s) of the guests are dispatched on one or plural real CPUs in the system using the S/370XA SIE (start interpretive execution) instruction. Special operations are provided, including the CPU alerting of other guests in different partitions using I/O interruption signalling. Interception is provided to handle special circumstances.

    10.
    发明专利
    未知

    公开(公告)号：DE3850181T2

    公开(公告)日：1995-01-12

    申请号：DE3850181

    申请日：1988-07-05

    Applicant: IBM

    Inventor： BEAN GEORGE HENRY ,  BORDEN TERRY LEE ,  FARRELL MARK STEVEN ,  GUM PETER HERMON ,  HOUGH ROGER ELDRED ,  JOHNSON FRANCIS EDWARD ,  MCCAULEY DONALD WILLIAM ,  RAKHMILEVICH MARK EMMANUEL ,  RATHJEN JOHN CORD ,  SCALZI CASPER ANTHONY ,  SCANLON JOHN FENTON ,  WYMAN LESLIE WOOD

    IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50 ,  G06F12/10

    Abstract: The embodiment discloses a method and means for partitioning the resources in a data processing system into a plurality of logical partitions. Host control code may be embodied in programming, microcode, or by special hardware to enable highly efficient operation of a plurality of preferred guest programming systems in the different partitions of the system. The main storage, expanded storage, the channel, and subchannel resources of a system are assigned to the different logical partitions in the system to enable a plurality of preferred guest programming systems to run simultaneously in the different partitions. This invention automatically relocates the absolute addresses of the I/O channel and subchannel resources in the system to their assigned partitions. Also the absolute and virtual addresses of the different guest programming systems are relocated into, as well as page addresses for any expanded storage, their assigned partitions. The guest programming systems generally will be different operating systems. The logical CPU(s) of the guests are dispatched on one or plural real CPUs in the system using the S/370XA SIE (start interpretive execution) instruction. Special operations are provided, including the CPU alerting of other guests in different partitions using I/O interruption signalling. Interception is provided to handle special circumstances.

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