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公开(公告)号：DE68923386T2
公开(公告)日：1996-03-28
申请号：DE68923386
申请日：1989-01-17
Applicant: IBM
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公开(公告)号：DE68923386D1
公开(公告)日：1995-08-17
申请号：DE68923386
申请日：1989-01-17
Applicant: IBM
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公开(公告)号：DE69231611D1
公开(公告)日：2001-02-01
申请号：DE69231611
申请日：1992-10-30
Applicant: IBM
Inventor： BAUM RICHARD IRWIN , PLAMBECK KENNETH ERNEST , SCALZI CASPER ANTHONY , SCHMALZ RICHARD JOHN , SINHA BHASKAR
Abstract: A method and means of translating a large logical address as a large virtual address (LVA) when dynamic address translator (DAT) is on and for using the large logical address as a large real address (LRA) when DAT (33) is off. This LVA or LRA is used for locating data and instructions in a computer memory. Each LVA is separated into three concatenated parts: a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and a low-order DAT VA part having the same size as the conventional type of virtual address. The low-order DAT VA part is translated by the associated translation table (48). This address translation of the low-order (DAT VA) part provides a real address that represents the translation of the LVA. The LVAs map into a large virtual address space (LVAS) represented by the sequence of valid ALEs in the set of ALs respectively represented by the sequence of valid ADEs in the AD. The sequence of ADEs in the AD respectively locate the ALs containing the ALEs which represent the LVAS. Thus, the range of LVAs (starting from zero) in the LVAS maps to the respective ALEs in the set of ALs. Each AL may contain a respective offset of ALEs that are not part of the LVAS.
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公开(公告)号：AT146886T
公开(公告)日：1997-01-15
申请号：AT90115517
申请日：1990-08-13
Applicant: IBM
Inventor： BLANDY GEOFFREY OWEN , EMMES DAVID BRUCE , HILL RONALD FRANKLIN , LINDQUIST DAVID BRUCE , PLAMBECK KENNETH ERNEST , SCALZI CASPER ANTHONY , SCHMALZ RICHARD JOHN
Abstract: A single non-privileged instruction copies a page of data from a source virtual address to a destination virtual address, regardless of which of plural electronic storage media contain the page locations, and without the intervention of any supervisory program when media and virtual addressing have been previously determined for the locations of the subject pages. The instruction is not required to specify which of the plural media it will use, does not require its user to know what backing media it will access, does not require main storage (MS) to be one of its backing media, and allows different types of physical addressing to be used by the different backing media. The instruction can lock any page for use in an MP. No physical direction of data movement is provided within the non-privileged machine instruction, which only designates virtual direction of movement. The separation of virtual direction from physical direction is done by avoiding instruction control over selection of electronic media. The non-privileged instruction can nevertheless express a preference for obtaining a copy of the destination page in an electronic medium in which the content of the page can be processed by further instructions. Also, the instruction can cause invocation of a privileged control program to avoid the need for a following condition code test instruction. A privileged instruction is also provided to wait for the completion of the unprivileged instruction and to invalidate a non-main storage (MS) medium page whether it is unlocked or locked, either correctly or incorrectly.
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Patent Agency Ranking
公开(公告)号：DE69231611T2
公开(公告)日：2001-07-05
申请号：DE69231611
申请日：1992-10-30
Applicant: IBM
Inventor： BAUM RICHARD IRWIN , PLAMBECK KENNETH ERNEST , SCALZI CASPER ANTHONY , SCHMALZ RICHARD JOHN , SINHA BHASKAR
Abstract: A method and means of translating a large logical address as a large virtual address (LVA) when dynamic address translator (DAT) is on and for using the large logical address as a large real address (LRA) when DAT (33) is off. This LVA or LRA is used for locating data and instructions in a computer memory. Each LVA is separated into three concatenated parts: a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and a low-order DAT VA part having the same size as the conventional type of virtual address. The low-order DAT VA part is translated by the associated translation table (48). This address translation of the low-order (DAT VA) part provides a real address that represents the translation of the LVA. The LVAs map into a large virtual address space (LVAS) represented by the sequence of valid ALEs in the set of ALs respectively represented by the sequence of valid ADEs in the AD. The sequence of ADEs in the AD respectively locate the ALs containing the ALEs which represent the LVAS. Thus, the range of LVAs (starting from zero) in the LVAS maps to the respective ALEs in the set of ALs. Each AL may contain a respective offset of ALEs that are not part of the LVAS.
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公开(公告)号：AT198381T
公开(公告)日：2001-01-15
申请号：AT92118610
申请日：1992-10-30
Applicant: IBM
Inventor： BAUM RICHARD IRWIN , PLAMBECK KENNETH ERNEST , SCALZI CASPER ANTHONY , SCHMALZ RICHARD JOHN , SINHA BHASKAR
Abstract: A method and means of translating a large logical address as a large virtual address (LVA) when dynamic address translator (DAT) is on and for using the large logical address as a large real address (LRA) when DAT (33) is off. This LVA or LRA is used for locating data and instructions in a computer memory. Each LVA is separated into three concatenated parts: a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and a low-order DAT VA part having the same size as the conventional type of virtual address. The low-order DAT VA part is translated by the associated translation table (48). This address translation of the low-order (DAT VA) part provides a real address that represents the translation of the LVA. The LVAs map into a large virtual address space (LVAS) represented by the sequence of valid ALEs in the set of ALs respectively represented by the sequence of valid ADEs in the AD. The sequence of ADEs in the AD respectively locate the ALs containing the ALEs which represent the LVAS. Thus, the range of LVAs (starting from zero) in the LVAS maps to the respective ALEs in the set of ALs. Each AL may contain a respective offset of ALEs that are not part of the LVAS.
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公开(公告)号：DE69029504T2
公开(公告)日：1997-07-17
申请号：DE69029504
申请日：1990-08-13
Applicant: IBM
Inventor： BLANDY GEOFFREY OWEN , EMMES DAVID BRUCE , HILL RONALD FRANKLIN , LINDQUIST DAVID BRUCE , PLAMBECK KENNETH ERNEST , SCALZI CASPER ANTHONY , SCHMALZ RICHARD JOHN
Abstract: A single non-privileged instruction copies a page of data from a source virtual address to a destination virtual address, regardless of which of plural electronic storage media contain the page locations, and without the intervention of any supervisory program when media and virtual addressing have been previously determined for the locations of the subject pages. The instruction is not required to specify which of the plural media it will use, does not require its user to know what backing media it will access, does not require main storage (MS) to be one of its backing media, and allows different types of physical addressing to be used by the different backing media. The instruction can lock any page for use in an MP. No physical direction of data movement is provided within the non-privileged machine instruction, which only designates virtual direction of movement. The separation of virtual direction from physical direction is done by avoiding instruction control over selection of electronic media. The non-privileged instruction can nevertheless express a preference for obtaining a copy of the destination page in an electronic medium in which the content of the page can be processed by further instructions. Also, the instruction can cause invocation of a privileged control program to avoid the need for a following condition code test instruction. A privileged instruction is also provided to wait for the completion of the unprivileged instruction and to invalidate a non-main storage (MS) medium page whether it is unlocked or locked, either correctly or incorrectly.
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公开(公告)号：DE69029504D1
公开(公告)日：1997-02-06
申请号：DE69029504
申请日：1990-08-13
Applicant: IBM
Inventor： BLANDY GEOFFREY OWEN , EMMES DAVID BRUCE , HILL RONALD FRANKLIN , LINDQUIST DAVID BRUCE , PLAMBECK KENNETH ERNEST , SCALZI CASPER ANTHONY , SCHMALZ RICHARD JOHN
Abstract: A single non-privileged instruction copies a page of data from a source virtual address to a destination virtual address, regardless of which of plural electronic storage media contain the page locations, and without the intervention of any supervisory program when media and virtual addressing have been previously determined for the locations of the subject pages. The instruction is not required to specify which of the plural media it will use, does not require its user to know what backing media it will access, does not require main storage (MS) to be one of its backing media, and allows different types of physical addressing to be used by the different backing media. The instruction can lock any page for use in an MP. No physical direction of data movement is provided within the non-privileged machine instruction, which only designates virtual direction of movement. The separation of virtual direction from physical direction is done by avoiding instruction control over selection of electronic media. The non-privileged instruction can nevertheless express a preference for obtaining a copy of the destination page in an electronic medium in which the content of the page can be processed by further instructions. Also, the instruction can cause invocation of a privileged control program to avoid the need for a following condition code test instruction. A privileged instruction is also provided to wait for the completion of the unprivileged instruction and to invalidate a non-main storage (MS) medium page whether it is unlocked or locked, either correctly or incorrectly.
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公开(公告)号：BR8900568A
公开(公告)日：1989-10-10
申请号：BR8900568
申请日：1989-02-09
Applicant: IBM
Inventor： BAUM RICHARD IRWIN , BORDEN TERRY LEE , BUTWELL JUSTIN RALPH , CLARK CARL EDWARD , GANEK ALAN GEORGE , LUM JAMES , MALL MICHAEL GERARD , PAGE DAVID RICHARD , PLAMBECK KENNETH ERNEST , SCALZI CASPER ANTHONY , SCHMALZ RICHARD JOHN
Abstract: A program authorization mechanism for authorizing access to an address space in the main memory of a computer system by a program being run under a multiple address space facility. An access-list entry is associated with each address space, each access-list entry being designated by an access-list-entry token contained in an access register. Each access-list entry includes a private indicator which indicates if the associated address space can be accessed by all programs from this access-list entry or if the associatd address space can only be accessed by an authorized program. For a program to be authorized, an extended authorization index in a control register must match an access-list extended authorization index in the access-list entry, or the extended authorization index value must be authorized in an authority table associated with the address space. An instruction for testing a given extended authorization index for a given access-list-entry is also disclosed.
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