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    Non-binary context mixing compressor/decompressor
    1.
    发明专利
    Non-binary context mixing compressor/decompressor 未知

    公开(公告)号：GB2574957A

    公开(公告)日：2019-12-25

    申请号：GB201913461

    申请日：2018-02-28

    Applicant: IBM

    Inventor： THOMAS PATRICK PARNELL ,  THOMAS MITTELHOLZER ,  TOBIAS BLAETTLER ,  CHARALAMPOS POZIDIS

    IPC: G06N3/08 ,  H03M7/30 ,  H04N19/91

    Abstract: A technique for non-binary context mixing in a compressor includes generating, by a plurality of context models, model predictions regarding a value of a next symbol to be encoded. A mixer generates a set of final predictions from the model predictions. An arithmetic encoder generates compressed data based on received input symbols and the set of final predictions. The received input symbols belong to an alphabet having a size greater than two and the mixer generates a feature matrix from the model predictions and trains a classifier that generates the set of final predictions.

    Multi-chip device and method for storing data
    2.
    发明专利
    Multi-chip device and method for storing data 未知

    公开(公告)号：GB2531756A

    公开(公告)日：2016-05-04

    申请号：GB201419240

    申请日：2014-10-29

    Applicant: IBM

    Inventor： TOBIAS BLAETTLER ,  THOMAS MITTELHOLZER ,  NIKOLAOS PAPANDREOU ,  THOMAS PARNELL ,  CHARALAMPOS POZIDIS ,  MILOS STANISAVLJEVIC

    IPC: G06F11/10

    Abstract: A multi-chip device 100 for storing data comprises: a plurality of memory chips 10 adapted to store encoded input data 1, where each of the chips includes a detection unit adapted to perform a detection algorithm on the stored encoded input data for retrieving detected bits and to output the retrieved detected bits 3 and detection information 2 associated with the detection algorithm; an evaluation unit 20 adapted to perform an evaluation of the detection information from each of the plurality of memory chips, and to adapt the detection algorithm of any of the detection units depending on the performed evaluation; a combination unit 30 adapted to receive the detected bits and to combine the detected bits; and a decoding unit 40 adapted to output decoded data by decoding the combined detected bits 5. The detection algorithm may be threshold based detection algorithm, such as a drift invariant detection algorithm. The device may facilitate improved bit error rates at the output of an error correction code engine, which may be particularly useful for non-volatile memory.

    Workload-adaptive data packing algorithm
    3.
    发明专利
    Workload-adaptive data packing algorithm 未知

    公开(公告)号：GB2554508B

    公开(公告)日：2019-01-16

    申请号：GB201711253

    申请日：2015-12-15

    Applicant: IBM

    Inventor： THOMAS PARNELL ,  CHARALAMPOS POZIDIS ,  THOMAS MITTELHOLZER ,  NIKOLAOS PAPANDREOU ,  CHARLES JOHN CAMP

    IPC: G06F11/10 ,  H03M13/13 ,  H03M13/15

    Abstract: A method, according to one embodiment, includes selecting, from a buffer, a combination of compressed logical pages of data to maximize an amount of used space in an error correction code container. The method also preferably includes processing the combination of compressed logical pages to generate error correction code data. Furthermore, the method may include writing the data corresponding to the combination of compressed logical pages and the associated error correction code data to a non-volatile random access memory. Other systems, methods, and computer program products are described in additional embodiments.

    Non-binary context mixing compressor/decompressor
    6.
    发明专利
    Non-binary context mixing compressor/decompressor 未知

    公开(公告)号：GB2574957B

    公开(公告)日：2020-08-19

    申请号：GB201913461

    申请日：2018-02-28

    Applicant: IBM

    Inventor： THOMAS PATRICK PARNELL ,  THOMAS MITTELHOLZER ,  TOBIAS BLAETTLER ,  CHARALAMPOS POZIDIS

    IPC: H03M7/30 ,  G06F3/06 ,  G06N3/04 ,  G06N3/08 ,  H04N19/91

    Abstract: A technique for non-binary context mixing in a compressor includes generating, by a plurality of context models, model predictions regarding a value of a next symbol to be encoded. A mixer generates a set of final predictions from the model predictions. An arithmetic encoder generates compressed data based on received input symbols and the set of final predictions. The received input symbols belong to an alphabet having a size greater than two and the mixer generates a feature matrix from the model predictions and trains a classifier that generates the set of final predictions.

    Combination error and erasure decoding for product codes
    8.
    发明专利
    Combination error and erasure decoding for product codes 未知

    公开(公告)号：GB2533501B

    公开(公告)日：2018-01-10

    申请号：GB201603366

    申请日：2014-07-28

    Applicant: IBM

    Inventor： ROY D CIDECIYAN ,  ROBERT A HUTCHINS ,  THOMAS MITTELHOLZER ,  KEISUKE TANAKA

    IPC: H03M13/29 ,  H03M13/15 ,  H03M13/37

    Abstract: In one embodiment, a method for combination error and erasure decoding for product codes includes receiving, using a hardware processor, captured data. The method also includes generating, using the hardware processor, erasure flags for the captured data and providing the erasure flags to a C2 decoder. Moreover, the method includes setting a stop parameter to be equal to a length of C1 codewords in a codeword interleave used to encode the captured data. In addition, the method includes selectively performing, in an iterative process, error or erasure C1 decoding followed by error or erasure C2 decoding until decoding is successful or unsuccessful. Other methods and computer program products are described in more embodiments.

    Workload-adaptive data packing algorithm
    10.
    发明专利
    Workload-adaptive data packing algorithm 未知

    公开(公告)号：GB2554508A

    公开(公告)日：2018-04-04

    申请号：GB201711253

    申请日：2015-12-15

    Applicant: IBM

    Inventor： THOMAS PARNELL ,  CHARALAMPOS POZIDIS ,  THOMAS MITTELHOLZER ,  NIKOLAOS PAPANDREOU ,  CHARLES JOHN CAMP

    IPC: G06F11/10 ,  H03M13/13 ,  H03M13/15

    Abstract: A method, according to one embodiment, includes selecting, from a buffer, a combination of compressed logical pages of data to maximize an amount of used space in an error correction code container. The method also preferably includes processing the combination of compressed logical pages to generate error correction code data. Furthermore, the method may include writing the data corresponding to the combination of compressed logical pages and the associated error correction code data to a non-volatile random access memory. Other systems, methods, and computer program products are described in additional embodiments.

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