公开(公告)号：EP4389279A1

公开(公告)日：2024-06-26

申请号：EP22215471.8

申请日：2022-12-21

Applicant: Imec VZW

Inventor： Zhang, Lei ,  Severi, Simone ,  Stakenborg, Tim ,  Labie, Riet ,  Soussan, Philippe ,  Karve, Gauri

IPC: B01L3/00

CPC classification number: B01L3/502707 ,  B01L2200/02520130101 ,  B01L2300/064520130101 ,  B01L2300/087420130101 ,  B01L2300/088720130101 ,  B01L2300/066320130101

Abstract: According to an aspect of the present inventive concept there is provided a microfluidic device comprising: at least one structure arranged in a pocket-defining layer defining a pocket in the pocket-defining layer; a semiconductor chip arranged in the pocket, the semiconductor chip comprising at least one electrode at the surface of the semiconductor chip; an electrical connection layer arranged above the semiconductor chip, wherein the electrical connection layer comprises electronic connections electrically connected to the at least one electrode and arranged to extend laterally in the electrical connection layer away from the semiconductor chip; at least one fluidic channel extending through the pocket-defining layer and above the semiconductor chip, the fluidic channel being arranged to be in fluidic communication with the at least one electrode.

公开(公告)号：EP2679537A1

公开(公告)日：2014-01-01

申请号：EP12173761.3

申请日：2012-06-27

Applicant: IMEC

Inventor： Severi, Simone ,  Van Hoof, Rita

IPC: B81C1/00

CPC classification number: B81C1/00611 ,  B81B2203/033 ,  B81B2207/07 ,  B81C2201/0121 ,  B81C2201/0132

Abstract: The present disclosure is related to a method for producing one or more structural elements (3,4) on top of at least two components of a Micro-Electromechanical System (MEMS) device, wherein a gap (10) is present between two of said components, the method comprising:
● filling said gap with a planarizing material,
● producing said elements on top of said two components (1,2),

wherein filling said gap (10) consists of performing subsequently:
● a first step, being a sputtering step or a combined sputtering/deposition step, thereby widening the entrance to said gap, and,
● a second step, being a conformal deposition step, thereby filling said gap with a planarizing material and producing a substantially flat layer (17) of said material on top of said components (1,2).

Abstract translation: 本公开涉及一种用于在微机电系统（MEMS）装置的至少两个部件的顶部上产生一个或多个结构元件（3,4）的方法，其中在所述两个所述 所述方法包括： - 用平坦化材料填充所述间隙， - 在所述两个部件（1,2）的顶部产生所述元件，其中填充所述间隙（10）包括随后执行： - 第一步骤 ，作为溅射步骤或组合的溅射/沉积步骤，从而扩大所述间隙的入口，以及作为共形沉积步骤的第二步骤，由此用平坦化材料填充所述间隙并产生基本平坦的层（ 所述材料在所述部件（1,2）的顶部上。

公开(公告)号：EP2277823A2

公开(公告)日：2011-01-26

申请号：EP10075263.3

申请日：2010-06-18

Applicant: IMEC ,  Katholieke Universiteit Leuven, K.U. Leuven R&D

Inventor： Jain, Ajay ,  Severi, Simone ,  Claes, Gert ,  Heck, John

IPC: B81C1/00

CPC classification number: B81C1/00246 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/07 ,  B81C2203/0714 ,  B81C2203/0735

Abstract: The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted.

Abstract translation: 本公开提出了用于制造MEMS器件的硅 - 锗层，并通过该硅 - 锗层接触的层之间的低电阻接触的方法，检查作为CMOS金属层或另一种硅 - 锗层，通过对开口 在介电层叠层分离两个层。 的层间形成在该开口中，从而覆盖在该开口的底部的另一个层的暴露表面上的开口的至少侧壁上。 这个中间层可以与所述硅 - 锗层接触包括TiN层。 这个中间层可以在TiN层和层之间进一步包括Ti层被接触。 在另一个实施例该中间层包括与所述硅 - 锗层接触的氮化钽层。 该中间层然后可以进一步包括在TaN层和所述层之间的Ta层被接触。

公开(公告)号：EP2618201B1

公开(公告)日：2015-11-04

申请号：EP12152010.0

申请日：2012-01-20

Applicant: IMEC

Inventor： Jayapala, Murali ,  Van Der Plas, Geert ,  Rochus, Veronique ,  Rottenberg, Xavier ,  Severi, Simone ,  Donnay, Stephane

IPC: G02B26/08 ,  G02B6/35

CPC classification number: G02B27/00 ,  G02B1/00 ,  G02B6/352 ,  G02B6/359 ,  G02B26/0825 ,  G02B26/0841 ,  G02B2207/00 ,  H04N1/00

公开(公告)号：EP2277823A3

公开(公告)日：2013-09-11

申请号：EP10075263.3

申请日：2010-06-18

Applicant: IMEC ,  Katholieke Universiteit Leuven, K.U. Leuven R&D

Inventor： Jain, Ajay ,  Severi, Simone ,  Claes, Gert ,  Heck, John

IPC: B81C1/00

CPC classification number: B81C1/00246 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/07 ,  B81C2203/0714 ,  B81C2203/0735

Abstract: The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted.

公开(公告)号：EP2113940A1

公开(公告)日：2009-11-04

申请号：EP08155510.4

申请日：2008-04-30

Applicant: IMEC

Inventor： Brunco, David ,  De Jaeger, Brice ,  Severi, Simone

IPC: H01L21/8238 ,  H01L21/265

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/28255 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/7833

Abstract: The invention is related to a method for producing one or more nMOSFET devices and one or more pMOSFET devices on the same semiconductor substrate (1) comprising a Si active area (2) and a Ge active area (3). The source and drain regions (5,6) in the Si area are formed by amorphisation and doping, followed by Solid Phase Epitaxial Regrowth (SPER). This enables low thermal budget processing compatible with the Ge device, including concurrent dopant activation in the Si and Ge areas.

Abstract translation: 本发明涉及在同一半导体衬底（1）上制造一个或多个nMOSFET器件和一个或多个pMOSFET器件的方法，该器件包括Si有源区（2）和Ge有源区（3）。 Si区域中的源区和漏区（5,6）通过非晶化和掺杂形成，随后是固相外延再生（SPER）。 这使得能够与Ge器件兼容的低热预算处理，包括Si和Ge区域中的并发掺杂剂激活。

公开(公告)号：EP2977606A1

公开(公告)日：2016-01-27

申请号：EP14178482.7

申请日：2014-07-25

Applicant: IMEC VZW

Inventor： Andrei, Alexandru ,  Severi, Simone

IPC: F04B19/00 ,  F04B43/00 ,  H01L21/00 ,  G01N21/00 ,  B01L3/00 ,  B01L9/00

CPC classification number: B01L3/502707 ,  F04B19/00

Abstract: A microfluidic device and method of manufacturing thereof are disclosed. In one embodiment, the microfluidic device includes a fluidic channel encapsulated in a solid container. Further, one wall of the fluidic channel is formed by an oxide. Furthermore, a surface of the solid container includes a first recess down to the oxide thereby allowing optical inspection of a fluid sample in the fluidic channel via the first recess, through the oxide.

Abstract translation: 公开了一种微流体装置及其制造方法。 在一个实施例中，微流体装置包括封装在固体容器中的流体通道。 此外，流体通道的一个壁由氧化物形成。 此外，固体容器的表面包括向下到氧化物的第一凹部，从而允许经由第一凹部通过氧化物光学检查流体通道中的流体样品。

公开(公告)号：EP2676923A1

公开(公告)日：2013-12-25

申请号：EP12172788.7

申请日：2012-06-20

Applicant: IMEC

Inventor： Severi, Simone ,  Verbist, Agnes

IPC: B81C1/00

CPC classification number: B81C1/00246 ,  B81B2201/0271 ,  B81B2207/015 ,  B81B2207/03 ,  B81C2203/0771 ,  G05D23/1928 ,  G05D23/20 ,  G05D23/24 ,  H03H3/0073 ,  H03H3/0076

Abstract: The invention is related to a method for producing parallel conductive lines on the surface of a MEMS device. In the method of the invention, a first conductive line is produced, followed by the deposition and planarization of a dielectric layer (such as an oxide layer), the formation of a trench in said dielectric layer, the filling of said trench with a conductive material and the planarization of said material, to obtain a second conductive line formed by the filled trench. The production technique allows to produce lines at a mutual distance of less than 500nm and having a width of less than 500nm, without losing the control over the width definition of the lines.

Abstract translation: 本发明涉及一种用于MEMS装置的表面上的生产传导平行线的方法。 在发明的方法中，第一导电线产生时，随之而来的是介电层的沉积和平坦化（颜色：诸如氧化层上），沟槽的所述介电层的形成，所述沟槽的填充有导电 材料和所述材料的平坦化，以获得由所述填充沟槽形成的第二导线。 生产技术允许在小于500nm的相互距离和具有小于500nm的宽度，以产生线条，而不会丢失在定义线的宽度的控制。

公开(公告)号：EP2618201A1

公开(公告)日：2013-07-24

申请号：EP12152010.0

申请日：2012-01-20

Applicant: IMEC

Inventor： Jayapala, Murali ,  Van Der Plas, Geert ,  Rochus, Veronique ,  Rottenberg, Xavier ,  Severi, Simone ,  Donnay, Stephane

IPC: G02B26/08 ,  G02B6/35

CPC classification number: G02B27/00 ,  G02B1/00 ,  G02B6/352 ,  G02B6/359 ,  G02B26/0825 ,  G02B26/0841 ,  G02B2207/00 ,  H04N1/00

Abstract: Described herein is a built-in self-calibration system and method for a micro-mirror array device, for example, operating as a variable focal length lens. The calibration method comprises determining a capacitance value for each micro-mirror element in the array device at a number of predetermined reference angles (530) to provide a capacitance-reference angle relationship (540). From the capacitance values, an interpolation step (550) is carried to determine intermediate tilt angles for each micro-mirror element in the array. A voltage sweep is applied to the micro-mirror array and capacitance values, for each micro-mirror element in the array, are measured (560). For a capacitance value that matches one of the values in the capacitance-reference angle relationship, the corresponding voltage is linked to the associated tilt angle to provide a voltage-tilt angle characteristic which then stored in a memory for subsequent use (570).

Abstract translation: 这里描述的是用于微镜阵列器件的内置自校准系统和方法，例如，作为可变焦距透镜操作。 校准方法包括以多个预定参考角度（530）确定阵列器件中每个微镜元件的电容值，以提供电容参考角度关系（540）。 根据电容值，进行内插步骤（550），以确定阵列中每个微镜元件的中间倾斜角度。 对微镜阵列施加电压扫描，测量阵列中每个微镜元件的电容值（560）。 对于与电容 - 参考角度关系中的一个值匹配的电容值，相应的电压与相关联的倾斜角度相关联，以提供随后存储在存储器中用于随后使用的电压 - 倾斜角特性（570）。

公开(公告)号：EP2416350A1

公开(公告)日：2012-02-08

申请号：EP10172129.8

申请日：2010-08-06

Applicant: IMEC

Inventor： Bryce, George ,  Severi, Simone ,  Verheyen, Peter

IPC: H01L21/285 ,  H01L21/768

CPC classification number: H01L21/28525 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76814 ,  H01L21/76879

Abstract: The present invention is related to a method for the selective deposition of a first semiconductor material on a substrate comprising a second semiconductor material and an insulator material, whereby the first semiconductor material is selectively deposited on the second semiconductor material, and wherein the method comprises the steps of a) pre-treating the substrate with a plasma produced from a carbon- and/or halogen-containing gas, and b) depositing the first semiconductor material on the substrate by chemical vapor deposition. In particular, the present invention is directed to an improved method for the manufacture of semiconducting devices features.

Abstract translation: 本发明涉及一种用于在包括第二半导体材料和绝缘体材料的衬底上选择性沉积第一半导体材料的方法，由此第一半导体材料被选择性地沉积在第二半导体材料上，并且其中该方法包括 步骤a）使用由含碳和/或含卤素气体产生的等离子体预处理所述衬底，以及b）通过化学气相沉积将所述第一半导体材料沉积在所述衬底上。 特别地，本发明涉及用于制造半导体器件特征的改进方法。