公开(公告)号：DE102004013926B4

公开(公告)日：2007-01-04

申请号：DE102004013926

申请日：2004-03-22

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BERGNER WOLFGANG ,  BEINTNER JOCHEN ,  CONTI RICHARD A ,  KNORR ANDREAS ,  WEIS ROLF

IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/94

Abstract: The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.

公开(公告)号：DE10307822B4

公开(公告)日：2005-08-18

申请号：DE10307822

申请日：2003-02-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS ,  DIVAKARUNI RAMACHANDRA ,  BEINTNER JOCHEN ,  MANDELMAN JACK

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8239

Abstract: Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

公开(公告)号：DE102004013928A1

公开(公告)日：2004-10-28

申请号：DE102004013928

申请日：2004-03-22

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BELYANSKY MICHAEL ,  GLUSCHENKOV OLEG ,  KNORR ANDREAS ,  PARKS CHRISTOPHER

IPC: H01L21/762 ,  H01L21/316 ,  H01L21/3105 ,  H01L21/8242

Abstract: A trench isolation structure is formed in a substrate. One or more openings are formed in a surface of the substrate, and a liner layer is deposited at least along a bottom and sidewalls of the openings. A layer of doped oxide material is deposited at least in the openings, and the substrate is annealed to reflow the layer of doped oxide material. Only a portion near the surface of the substrate is removed from the layer of doped oxide material in the opening. A cap layer is deposited atop a remaining portion of the layer of doped oxide material in the opening.

公开(公告)号：DE102004013926A1

公开(公告)日：2004-10-21

申请号：DE102004013926

申请日：2004-03-22

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BERGNER WOLFGANG ,  BEINTNER JOCHEN ,  CONTI RICHARD A ,  KNORR ANDREAS ,  WEIS ROLF

IPC: H01L21/8242 ,  H01L29/94 ,  H01L27/108

Abstract: The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.

公开(公告)号：DE10354717B4

公开(公告)日：2006-09-14

申请号：DE10354717

申请日：2003-11-22

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  ECONOMIKOS LAERTIS ,  KNORR ANDREAS ,  WISE MICHAEL L

IPC: H01L21/304 ,  H01L21/768 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/461 ,  H01L21/8242

Abstract: CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.

公开(公告)号：DE102004001099A1

公开(公告)日：2004-07-22

申请号：DE102004001099

申请日：2004-01-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BELYANSKY MICHAEL ,  GLUSCHENKOV OLEG ,  KNORR ANDREAS

IPC: C23C8/36 ,  H01L21/316

Abstract: A method of oxidizing a substrate having area of about 30,000 mm 2 or more. The surface is preferably comprised of silicon-containing materials, such as silicon, silicon germanium, silicon carbide, silicon nitride, and metal silicides. A mixture of oxygen-bearing gas and diluent gas normally non-reactive to oxygen, such as Ne, Ar, Kr, Xe, and/or Rn are ionized to create a plasma having an electron density of at least about 1 e12 cm -3 and containing ambient electrons having an average temperature greater than about 1 eV. The substrate surface is oxidized with energetic particles, comprising primarily atomic oxygen, created in the plasma to form an oxide film of substantially uniform thickness. The oxidation of the substrate takes place at a temperature below about 700° C., e.g., between about room temperature, 20° C., and about 500° C.

公开(公告)号：DE10307822A1

公开(公告)日：2003-11-06

申请号：DE10307822

申请日：2003-02-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS ,  DIVAKARUNI RAMACHANDRA ,  BEINTNER JOCHEN ,  MANDELMAN JACK

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8239

Abstract: Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

公开(公告)号：DE10354717A1

公开(公告)日：2004-07-15

申请号：DE10354717

申请日：2003-11-22

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  ECONOMIKOS LAERTIS ,  KNORR ANDREAS ,  WISE MICHAEL L

IPC: H01L21/304 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/461 ,  H01L21/768 ,  H01L21/8242

Abstract: CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.

公开(公告)号：WO0243111A3

公开(公告)日：2002-08-01

申请号：PCT/EP0113436

申请日：2001-11-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MALIK RAJEEV ,  SEITZ MIHEL ,  KNORR ANDREAS

IPC: H01L21/762 ,  H01L21/8242

CPC classification number: H01L21/76229 ,  H01L27/1087

Abstract: A method for forming isolation trenches for semiconductor devices forms, in a substrate, a plurality of trenches (30 and 32) having different widths including widths above a threshold size (30) and widths below a threshold size (32). The plurality of trenches have a same first depth (D1). A masking layer (52) is deposited in the plurality of trenches, the masking layer has a thickness sufficient to both line the trenches with the widths above the threshold size and completely fill the trenches with the widths below the threshold size. A portion of the substrate (16) is exposed at a bottom of the trenches with the widths above the threshold size by etching the masking layer. The plurality of trenches are etched to extend the trenches with the widths above the threshold size to a greater depth (D2).

Abstract translation: 一种用于形成半导体器件的隔离沟槽的方法在衬底中形成具有不同宽度的多个沟槽（30和32），所述宽度包括高于阈值尺寸（30）和低于阈值尺寸（32）的宽度。 多个沟槽具有相同的第一深度（D1）。 在多个沟槽中沉积掩模层（52），掩模层的厚度足以使沟槽的宽度高于阈值尺寸，并且完全填充宽度低于阈值尺寸的沟槽。 通过蚀刻掩模层，衬底（16）的一部分在沟槽的底部暴露，其宽度高于阈值尺寸。 蚀刻多个沟槽以使沟槽的宽度高于阈值尺寸延伸到更大的深度（D2）。

公开(公告)号：DE10360537B4

公开(公告)日：2008-02-14

申请号：DE10360537

申请日：2003-12-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS ,  WISE MICHAEL

IPC: H01L21/762 ,  H01L27/108

Abstract: A method of forming deep isolation trenches in the fabrication of ICs is disclosed. The substrate is prepared with deep isolation trenches. The isolation trenches are partially filled with a first dielectric material. An etch mask layer is deposited on the substrate and used to remove excess first dielectric material on the surface of the substrate. The isolation trenches are then completely filled with a second dielectric material. Excess second dielectric material is then removed from the surface of the substrate.