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    CTE MATCHED INTERPOSER AND METHOD OF MAKING
    1.
    发明申请
    CTE MATCHED INTERPOSER AND METHOD OF MAKING 审中-公开
    CTE匹配插件及其制作方法

    公开(公告)号：WO2013154497A4

    公开(公告)日：2014-01-23

    申请号：PCT/SE2013050408

    申请日：2013-04-15

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： EBEFORS THORBJOERN ,  PERTTU DANIEL

    IPC: H01L23/32 ,  H01L23/498 ,  H01L23/52 ,  H01L23/538

    CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: The inventive merit of the present interposer is that it is possible to taylor the coefficient of thermal expansion CTE of the interposer to match components to be attached thereto within very wide ranges. The invention relates to a emiconductor interposer, comprising a substrate (10) of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer- through via (18, 28, 27) comprising metal (27). At least one recess (20)is provided in the first side of the substrate (10) and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure (20). The exposed surfaces of the metal filled via and the metal filled recess (18, 27) are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via (18, 28, 27) comprises a narrow part (18) and a wider part (27), and there are provided contact elements on said routing structure (20) having an aspect ratio, height:diameter,

    Abstract translation: 本插值器的优点在于，可以在非常宽的范围内使插入件的热膨胀系数CTE与要附着的部件相匹配。 本发明涉及一种具有第一侧（FS）和相对的第二侧（BS）的半导体材料的衬底（10）的半导体插入器。 存在至少一个包含金属（27）的导电晶片通孔（18,28,27）。 至少一个凹部（20）设置在基板（10）的第一侧面中，并且在基板的半导体材料中，凹槽填充有金属并与晶圆通孔连接，从而提供布线结构（20）。 填充通孔的金属和金属填充的凹槽（18,27）的暴露的表面基本上与衬底的第一侧上的衬底表面齐平。 晶片通孔（18,28,27）包括窄部分（18）和较宽部分（27），并且在所述布线结构（20）上设置有具有纵横比，高度：直径， 1：1，优选1：1至2：1。

    CTE MATCHED INTERPOSER AND METHOD OF MAKING
    2.
    发明申请
    CTE MATCHED INTERPOSER AND METHOD OF MAKING 审中-公开
    CTE匹配插件及其制作方法

    公开(公告)号：WO2013154497A3

    公开(公告)日：2013-12-05

    申请号：PCT/SE2013050408

    申请日：2013-04-15

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： EBEFORS THORBJOERN ,  PERTTU DANIEL

    IPC: H01L23/32 ,  H01L23/498 ,  H01L23/52 ,  H01L23/538

    CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: The inventive merit of the present interposer is that it is possible to taylor the coefficient of thermal expansion CTE of the interposer to match components to be attached thereto within very wide ranges. The invention relates to a emiconductor interposer, comprising a substrate (10) of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer- through via (18, 28, 27) comprising metal (27). At least one recess (20)is provided in the first side of the substrate (10) and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure (20). The exposed surfaces of the metal filled via and the metal filled recess (18, 27) are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via (18, 28, 27) comprises a narrow part (18) and a wider part (27), and there are provided contact elements on said routing structure (20) having an aspect ratio, height:diameter,

    Abstract translation: 本插值器的优点在于，可以在非常宽的范围内使插入件的热膨胀系数CTE与要附着的部件匹配。 本发明涉及一种具有第一侧（FS）和相对的第二侧（BS）的半导体材料的衬底（10）的半导体插入器。 存在包含金属（27）的至少一个导电晶片通孔（18,28,27）。 在衬底（10）的第一侧中提供至少一个凹部（20），并且在衬底的半导体材料中，凹部填充有金属并与晶片通孔连接，从而提供路由结构（20）。 金属填充通孔和金属填充凹槽（18,27）的暴露表面基本上与衬底的第一侧上的衬底表面齐平。 晶片通孔（18,28,27）包括窄部分（18）和较宽部分（27），并且在所述布线结构（20）上设置有具有纵横比，高度：直径， 1：1，优选1：1至2：1。

    ELECTROLESS METAL THROUGH SILICON VIA
    5.
    发明申请
    ELECTROLESS METAL THROUGH SILICON VIA 审中-公开
    通过硅通孔的化学镀金属

    公开(公告)号：WO2014051511A2

    公开(公告)日：2014-04-03

    申请号：PCT/SE2013051124

    申请日：2013-09-27

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： EBEFORS THORBJOERN ,  KNUTSSON HENRIK

    CPC classification number: H01L21/76897 ,  H01L21/0217 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/288 ,  H01L21/76847 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76888 ,  H01L21/76892 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The invention relates to methods of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface. It comprises providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The the poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectiveley deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited Cu on the Ni by a plating process. Line widths and spacings

    Abstract translation: 本发明涉及制造半导体衬底中具有高纵横比的衬底贯穿金属通孔和衬底表面上的金属图案的方法。 它包括提供半导体衬底（晶片）并在衬底上沉积多晶硅。 通过蚀刻掉不需要的部分来图案化衬底表面上的多晶硅。 然后，通过无电处理将Ni选择性地沉积在多晶硅上。 穿过基板形成通孔，其中孔中的壁受到与上述相同的处理。 通过电镀工艺将Cu沉积在Ni上。 晶圆两侧的线宽和间距<10μm。

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