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    2.
    发明专利
    未知

    公开(公告)号：DE69633000D1

    公开(公告)日：2004-09-02

    申请号：DE69633000

    申请日：1996-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TASSAN CASER FABIO ,  SALI MAURO ,  CANE MARCELLO

    IPC: G11C8/10 ,  G11C16/08 ,  G11C11/00 ,  G11C16/06 ,  G11C8/00

    Abstract: The invention relates to a row decoding circuit (1) for an electrically programmable and erasable semiconductor non-volatile storage device of the type which comprises a matrix (2) of memory cells laid out as cell rows (WL) and columns and is divided into sectors, said circuit being input row decode signals (p,ly,lx,ls) and supply voltages (Vpcxs, pgate) in order to drive an output stage (8) incorporating a complementary pair of high-voltage MOS transistors (M15,M13) of the pull-up and pull-down type, respectively, which are connected to form an output terminal (U) connected to the rows (WL) of one sector of the matrix (2), characterized in that a MOS transistor (M9) of the P-channel depletion type with enhanced gate oxide is provided between the output terminal (U) and the pull-down transistor (M13). The control terminal of the depletion transistor (M9) forms a further input (H) of the circuit (1).

    3.
    发明专利
    未知

    公开(公告)号：DE69725977D1

    公开(公告)日：2003-12-11

    申请号：DE69725977

    申请日：1997-08-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROSSI ANNAMARIA ,  FUCILI GIONA ,  CANE MARCELLO ,  NESSI MAURIZIO

    IPC: H03K3/037 ,  H03K3/356 ,  H03K3/00

    Abstract: A toggle flip-flop (FFT) with reduced integration area, comprising a flip-flop of the D type with an inverting input stage (T,A,B,C) and a master-slave portion. Three transistors (M1,M2,M3) connected to the inverting stage form a logic gate of the XOR type whereto the output terminal (Q) of the master-slave portion is fed back.

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