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    ROW DECODING CIRCUIT FOR ELECTRONIC MEMORY DEVICE AND METHOD OF CONTROLLING ROW DECODING STEP
    1.
    发明专利
    ROW DECODING CIRCUIT FOR ELECTRONIC MEMORY DEVICE AND METHOD OF CONTROLLING ROW DECODING STEP 失效

    公开(公告)号：JPH11260083A

    公开(公告)日：1999-09-24

    申请号：JP37435898

    申请日：1998-12-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI ,  FERRARIO DONATO ,  GHEZZI STEFANO

    IPC: G11C16/06 ,  G11C8/08 ,  G11C11/408

    Abstract: PROBLEM TO BE SOLVED: To enable accurate operation in different conditions by providing a cascade-connected inverter of a hierarchical structure, a circuit for dynamically increasing step by step a read voltage level, a first means for increasing a read voltage level to a particular voltage and a second means for increasing a read voltage level to the other particular voltage. SOLUTION: A first means increases a read voltage level to a value equal to the supply voltage + threshold voltage and a second means increases a read voltage level to a value equal to the supply voltage +2 × threshold voltage. A memory row is selected by simultaneously setting the pre-decoding signals LX, LY, LZ and P to high logical values to form a first decoding final inverter 15 provided with the transistors M9 and M10. The voltage supplied to the designated rows of address is boosted to Vcc+2Vtp. In the rows not designated, the voltage Vcc+Vtp is transferred to the center node Xc of the transistors M9 and M10.

    METHOD AND CIRCUIT FOR ADJUSTING LENGTH OF ATD PULSE SIGNAL
    2.
    发明专利
    METHOD AND CIRCUIT FOR ADJUSTING LENGTH OF ATD PULSE SIGNAL 失效

    公开(公告)号：JPH11219590A

    公开(公告)日：1999-08-10

    申请号：JP31506698

    申请日：1998-11-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  ZAMMATTIO MATTEO ,  FERRARIO DONATO

    IPC: G11C11/41 ,  G11C8/18

    Abstract: PROBLEM TO BE SOLVED: To provide the method and circuit for adjusting the duration time of an ATD signal pulse which have respectively a functional feature and a structural feature capable of eliminating defects accompanying possible solution by conventional technology. SOLUTION: In this method and circuit for adjusting a pulse synchronizing signal ATD about the reading phase of a memory cell in a semiconductor integrated electronic memory device, a pulse signal ATD is generated in accordance with detecting variation of at least one logic state of plural address input terminals of a memory cell, and an equalizing signal SAEQ for a sense amplifier is also generated. When row voltage reaches the prescribed value being sufficient for realizing highly reliable reading by row voltage, the SAEQ pulse is interrupted (STOP). It is profitable that the interruption of the pulse is caused by the logic signal STOP activated in accordance with exceeding the prescribed voltage value during over-boosting phase of a row of an addressed memory.

    3.
    发明专利
    未知

    公开(公告)号：DE69727937D1

    公开(公告)日：2004-04-08

    申请号：DE69727937

    申请日：1997-11-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  ZAMMATTIO MATTEO ,  FERRARIO DONATO

    IPC: G11C11/41 ,  G11C8/18 ,  G11C8/00 ,  G11C7/00

    Abstract: The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier. The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.

    6.
    发明专利
    未知

    公开(公告)号：DE60015916D1

    公开(公告)日：2004-12-23

    申请号：DE60015916

    申请日：2000-02-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GHEZZI STEFANO ,  FERRARIO DONATO ,  YERO EMILIO ,  CAMPARDO GIOVANNI

    IPC: H03K19/177

    Abstract: A programmable logic array (PLA) has at least an AND plane comprising an array of transistors arranged in rows and columns, the transistors belonging to a same column being connected in series with each other, the two end current terminals of said series of transistors being coupled to the supply voltage rail (VDD) and to a reference (GND), respectively, the transistors of the first row and of the last row of the array having their control terminals coupled to respective opposite enabling/disabling potentials. To each row of said array, with the exception of the first and the last row, are associated three control lines, the first line being coupled to a first input value, the second line being coupled to the inverted logic value of the first input value and the third line being coupled to a voltage sufficient to keep in a state of conduction the transistors of the row connected to it. Each transistor of each row except the first and the last row has its control terminal connected to one of the three control lines associated to the row. An OR plane comprises at least an array of transistors arranged in rows and columns, the transistors belonging to a same column having their respective control terminals connected to a control line and a first current terminal coupled to a reference potential (GND), each transistor of each row of the array having a second current terminal connected or not to a respective output line. The second current terminal of each transistor of the array that is not connected to a respective output line is short-circuited to the first current terminal of the same transistor.

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