公开(公告)号：JP2001028197A

公开(公告)日：2001-01-30

申请号：JP2000196290

申请日：2000-06-26

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  ZAMMATTIO MATTEO ,  CAMPARDO GIOVANNI

IPC: G11C16/06 ,  G11C8/12 ,  G11C16/12

Abstract: PROBLEM TO BE SOLVED: To provide bias to a plurality of memory sectors in a memory element by bulk of a smaller region in a non-volatile memory element of especially a flash type and providing method for bias in a memory element. SOLUTION: A memory element 21 having a plurality of memory sectors 15 each sector of which includes a plurality of memory cells 1 is provided with a hierarchical sector decoding means. One group out of a plurality of groups of bias lines 28-32 is provided to each sector row, and is extended in parallel to a sector row. Each of a plurality of sector switching stages 35 is connected between a corresponding memory sector and a group corresponding to a bias line. A sector switching stage connected to memory sectors arranged in the same sector column is controlled by the same control signals S0, S1 supplied to a control line 40 extending in parallel to a sector column.

公开(公告)号：JPH11219590A

公开(公告)日：1999-08-10

申请号：JP31506698

申请日：1998-11-05

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  ZAMMATTIO MATTEO ,  FERRARIO DONATO

IPC: G11C11/41 ,  G11C8/18

Abstract: PROBLEM TO BE SOLVED: To provide the method and circuit for adjusting the duration time of an ATD signal pulse which have respectively a functional feature and a structural feature capable of eliminating defects accompanying possible solution by conventional technology. SOLUTION: In this method and circuit for adjusting a pulse synchronizing signal ATD about the reading phase of a memory cell in a semiconductor integrated electronic memory device, a pulse signal ATD is generated in accordance with detecting variation of at least one logic state of plural address input terminals of a memory cell, and an equalizing signal SAEQ for a sense amplifier is also generated. When row voltage reaches the prescribed value being sufficient for realizing highly reliable reading by row voltage, the SAEQ pulse is interrupted (STOP). It is profitable that the interruption of the pulse is caused by the logic signal STOP activated in accordance with exceeding the prescribed voltage value during over-boosting phase of a row of an addressed memory.

公开(公告)号：DE69921974D1

公开(公告)日：2004-12-23

申请号：DE69921974

申请日：1999-06-24

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  ZAMMATTIO MATTEO ,  CAMPARDO GIOVANNI

IPC: G11C16/06 ,  G11C8/12 ,  G11C16/12 ,  G11C16/16 ,  G11C16/08

Abstract: The memory device (21) has hierarchical sector decoding (24, 25). A plurality of groups of supply lines (28-32) is provided, one for each sector row, extending parallel to the sector rows. A plurality of switching stages (35) are each connected between a respective sector (15) and a respective group of supply lines (28-32); the switching stages (35) connected to sectors (15) arranged on a same column are controlled by same control signals (S0, S1) supplied on control lines (40) extending parallel to the columns of sectors. For biasing the sectors, modification voltages (NW, SB, VNEG) are sent to at least one selected group of biasing lines (28-32), and control signals (SO, S1) are sent to the switching stages connected to a selected sector column.

公开(公告)号：DE69727937D1

公开(公告)日：2004-04-08

申请号：DE69727937

申请日：1997-11-05

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  ZAMMATTIO MATTEO ,  FERRARIO DONATO

IPC: G11C11/41 ,  G11C8/18 ,  G11C8/00 ,  G11C7/00

Abstract: The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier. The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.

公开(公告)号：DE69621020T2

公开(公告)日：2002-10-24

申请号：DE69621020

申请日：1996-11-04

Applicant: ST MICROELECTRONICS SRL

Inventor： MACCARRONE MARCO ,  ZAMMATTIO MATTEO ,  COMMODARO STEFANO

IPC: G05F3/26 ,  G05F3/30

Abstract: A band-gap reference voltage generator comprises an operational amplifier (2) comprising a first input and a second input, the first input being coupled to a first feedback network (4) and the second input being coupled to a second feedback network (6) both coupled to an output (7) of the operational amplifier providing a reference voltage, the first feedback network containing an emitter-base junction of first bipolar junction transistor means (Q1) and the second feedback network containing an emitter-base junction of second bipolar junction transistor means (Q2), and current supplying means (11) for supplying a bias current to the operational amplifier, the current supplying means being deactivatable in a substantially zero power consumption operating condition for turning the reference voltage generator off, characterized by comprising start-up circuit means (13) activated upon start-up of the reference voltage generator for a fixed, prescribed time interval for forcing a start-up current to flow through the first bipolar junction transistor means (Q1).

公开(公告)号：DE69615149D1

公开(公告)日：2001-10-18

申请号：DE69615149

申请日：1996-03-06

Applicant: ST MICROELECTRONICS SRL

Inventor： GOLLA CARLA MARIA ,  ZAMMATTIO MATTEO ,  ZANARDI STEFANO

IPC: G11C8/18 ,  H03K5/1534 ,  H03K3/011 ,  H03K3/355 ,  G11C8/00

Abstract: An address transition detection circuit (30) having a number of cells (1) supplied with respective address signals and output connected in a wired NOR configuration to generate a pulse signal (WN) on detecting transitions of their respective address signals. The pulse signal is supplied to a source stage for generating an address transition signal (ATDO) having a first and second switching edge on receiving the pulse signal. The source stage has a monostable stage (80) for generating an end-of-transition signal (ATDY) with a predetermined delay following reception of the pulse signal; and an output stage (35, 70) connected to the cells (1) and to the monostable stage (80), which generates the first switching edge of the address transition signal (ATDO) on receiving the pulse signal (WN), and the second switching edge on receiving the end-of-transition signal. The monostable stage (80) presents a compensating structure (40, 42, 44) for maintaining the delay in the switching of the end-of-transition signal (ATDY) stable alongside variations in temperature and supply voltage.

公开(公告)号：DE69728148D1

公开(公告)日：2004-04-22

申请号：DE69728148

申请日：1997-11-05

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  MACCARRONE MARCO ,  ZAMMATTIO MATTEO

IPC: G11C8/18 ,  G11C8/00

公开(公告)号：DE69739284D1

公开(公告)日：2009-04-16

申请号：DE69739284

申请日：1997-11-05

Applicant: ST MICROELECTRONICS SRL

Inventor： MULATTI JACOPO ,  ZAMMATTIO MATTEO ,  GHILARDELLI ANDREA ,  CARRERA MARCELLO

IPC: G05F1/00 ,  G05F3/24

公开(公告)号：DE69935919D1

公开(公告)日：2007-06-06

申请号：DE69935919

申请日：1999-12-30

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMMATTIO MATTEO ,  MOTTA ILARIA ,  MICHELONI RINO ,  GOLLA CARLA

IPC: G11C16/30 ,  G11C5/14

Abstract: A voltage boost device includes a first boost stage (4) and a second boost stage (5) connected to an input terminal and to an output terminal (10), the output terminal (10) supplying an output voltage higher than a supply voltage. The input terminal receives an operating condition signal (SB) having a first logic level representative of a standby operating state and a second logic level representative of an active operation state. The first boost stage (4) is enabled in presence of the second logic level of the operating condition signal (SB), and is disabled in presence of the first logic level of the operating condition signal (SB); the second boost stage (5) is controlled in a first operating condition in presence of the first logic level of the operating condition signal (SB), and is controlled in a second operating condition in presence of the second logic level of the operating condition signal (SB).

公开(公告)号：DE69615149T2

公开(公告)日：2002-07-04

申请号：DE69615149

申请日：1996-03-06

Applicant: ST MICROELECTRONICS SRL

Inventor： GOLLA CARLA MARIA ,  ZAMMATTIO MATTEO ,  ZANARDI STEFANO

IPC: G11C8/18 ,  H03K5/1534 ,  H03K3/011 ,  H03K3/355 ,  G11C8/00

Abstract: An address transition detection circuit (30) having a number of cells (1) supplied with respective address signals and output connected in a wired NOR configuration to generate a pulse signal (WN) on detecting transitions of their respective address signals. The pulse signal is supplied to a source stage for generating an address transition signal (ATDO) having a first and second switching edge on receiving the pulse signal. The source stage has a monostable stage (80) for generating an end-of-transition signal (ATDY) with a predetermined delay following reception of the pulse signal; and an output stage (35, 70) connected to the cells (1) and to the monostable stage (80), which generates the first switching edge of the address transition signal (ATDO) on receiving the pulse signal (WN), and the second switching edge on receiving the end-of-transition signal. The monostable stage (80) presents a compensating structure (40, 42, 44) for maintaining the delay in the switching of the end-of-transition signal (ATDY) stable alongside variations in temperature and supply voltage.