公开(公告)号：EP0793273B1

公开(公告)日：2003-12-10

申请号：EP96830086.3

申请日：1996-02-28

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Claudio ,  Ginami, Giancarlo ,  Daffra, Stefano ,  Ravaglia, Andrea ,  Cereda, Manlio Sergio

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/115

公开(公告)号：EP1058304A1

公开(公告)日：2000-12-06

申请号：EP99830336.6

申请日：1999-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76885 ,  H01L2924/3011

Abstract: An improved method for autoaligning lines (WL) of a conductive material in circuits integrated on a semiconductor substrate (2), comprising the following steps:

forming, on said semiconductor substrate (2), a plurality of regions (3) projecting from the substrate (2) surface and aligned to one another;
forming a fill layer (4) in the gaps between said regions (3) ;
planarizing said fill layer (4) to expose said regions (3) ;
removing a surface portion of said regions (3) to form holes (5) at the locations of said regions (3);
forming an insulating layer (6) in said holes (5);
selectively removing the dielectric layer (6) to form spacers (7) along the edges of said holes (5) ;
depositing at least one conductive layer (8) all over the exposed surface;
photolithographing with a mask and etching away the layer (8) to define lines (WL) and collimate them to the underlying regions (3).

Abstract translation: 形成，在所述半导体衬底（2），（3）从所述基板突出区域的多元性：用于autoaligning的导电材料线（WL）的集成（2）上，其包括以下步骤的半导体衬底的电路的改进的方法 （2）表面和彼此对齐; 在形成所述区域之间的间隙的填充层（4）（3）; 所述填充平坦化层（4），以露出所述区域（3）; 去除所述的区域的表面部分（3），以形成孔（5），在所述区域的位置（3）; 上形成绝缘层（6）在所述孔（5）; 选择性地去除所述电介质层（6），以形成间隔物（7）沿所述孔的边缘（5）; 沉积至少一层导电层（8）在整个暴露的表面; 用掩模photolithographing并蚀刻掉层（8），以限定线（WL），并将它们准直到底层区域（3）。

公开(公告)号：EP0902466A1

公开(公告)日：1999-03-17

申请号：EP97830428.5

申请日：1997-08-27

Applicant: STMicroelectronics S.r.l.

Inventor： Cassio, Valerio ,  Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo

IPC: H01L21/8239 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11541 ,  H01L27/11543

Abstract: A method of manufacturing a P-channel native MOS transistor (7) in a circuit integrated on a semiconductor (1) which also includes a matrix of non-volatile memory cells of the floating gate type with two polysilicon levels (5,10) having an interpoly dielectric layer sandwiched between the two polysilicon levels, comprises the following steps:

masking and defining active areas (2) of the discrete integrated devices;
masking and defining the first polysilicon level (5) using a Poly1 mask; and
masking and defining an intermediate dielectric layer (8) using a Matrix mask (9).

The length of the native threshold channel of the native transistor is defined by means of the Matrix mask (9) and by etching away the interpoly dielectric layer (8). A subsequent step of masking and defining the second polysilicon level (10) provides for the use of a Poly2 mask (12) which extends the active area of the transistor (7) with a greater width than the previous mask (9) in order to enable, by subsequent etching, the two polysilicon levels (5,10) to overlap in self-alignment over the channel region.

Abstract translation: 一种在集成在半导体（1）上的电路中制造P沟道天然MOS晶体管（7）的方法，该半导体还包括具有两个多晶硅层（5,10）的浮置型的非易失性存储单元的矩阵， 夹在两个多晶硅层之间的多晶硅介电层包括以下步骤：屏蔽和限定离散集成器件的有源区域（2）; 使用Poly1掩模掩蔽和限定第一多晶硅层（5）; 以及使用矩阵掩模（9）掩蔽和限定中间介电层（8）。 通过矩阵掩模（9）和蚀刻掉多晶硅介电层（8）来限定天然晶体管的天然阈值通道的长度。 掩蔽和限定第二多晶硅层（10）的后续步骤提供使用Poly2掩模（12），其以比先前的掩模（9）更大的宽度延伸晶体管（7）的有源区域，以便 通过随后的蚀刻使得两个多晶硅层（5,10）能够在沟道区域上自对准重叠。

公开(公告)号：EP0892430A1

公开(公告)日：1999-01-20

申请号：EP97830359.2

申请日：1997-07-16

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Ginami, Giancarlo

IPC: H01L21/8247 ,  H01L27/115 ,  H01L23/528

CPC classification number: H01L27/11526 ,  H01L23/5283 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11543 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer (6) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer (8); c) forming over the whole integrated circuit a first layer of conductive material (9); d) forming over the first layer of conductive material (9) a layer of insulating material (10); e) removing the layer of insulating material (10) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material (11) which in the memory cell array area is separated from the first layer of conductive material (9) by the insulating material layer (10), while outside the memory cell array area is directly superimposed over said first layer of conductive material (9); g) inside the memory cell array area, defining first strips (22) of the second layer of conductive material (11) for forming rows (3) of the memory cell array (1), and outside the memory cell array area defining second strips (17) of the second layer of conductive material (11) for forming interconnection lines (100) for electrically interconnecting the rows (3) of the memory cell array with a circuitry (5,RD), said defining the second strips (17) providing for selectively etching the first and second layers of conductive material (9,11) outside the memory cell array area by means of a first mask (MASK1), and said defining the first strips (22) providing for selectively etching the second layer of conductive material (11), the layer of insulating material (10) and the first layer of conductive material (9) inside the memory cell array area by means of a second mask (MASK2). The first and second masks (MASK1,MASK2) overlap in a boundary region around the memory cell array area, so that the first strips (22) and the second strips (17) of the second layer of conductive material (11) are automatically joined at respective ends thereof at said boundary region.

Abstract translation: 一种用于制造集成电路的方法，包括存储单元阵列，提供：a）在半导体层（6）的存储单元阵列区域中形成用于存储单元的有效区域; b）在所述存储单元的所述有源区上形成栅极氧化物层（8）; c）在整个集成电路上形成第一层导电材料（9）; d）在第一层导电材料（9）上形成一层绝缘材料（10）; e）从存储单元阵列区域的外部去除绝缘材料层（10）; f）在整个集成电路上形成第二层导电材料（11），其在存储单元阵列区域中通过绝缘材料层（10）与第一导电材料层（9）分离，而在存储单元外部 阵列区域直接叠加在所述第一导电材料层（9）上; g）在存储单元阵列区域内部，限定用于形成存储单元阵列（1）的行（3）的第二导电材料层（11）的第一条带（22），以及限定第二条带 用于形成用于将存储单元阵列的行（3）与电路（5，RD）电气互连的互连线（100）的第二层导电材料（11）的第一层（17），所述第二层导电材料（11） 提供通过第一掩模（MASK1）选择性地蚀刻存储器单元阵列区域外的第一和第二导电材料层（9,11），并且所述第一条带（22）提供用于选择性地蚀刻第二层 导电材料（11），绝缘材料层（10）和第一层导电材料（9）通过第二掩模（MASK2）在存储单元阵列区域内。 第一和第二掩模（MASK1，MASK2）在存储单元阵列区域周围的边界区域中重叠，使得第二导电材料层（11）的第一条带（22）和第二条带（17）自动连接 在其各个端部处于所述边界区域。

公开(公告)号：EP0902465B1

公开(公告)日：2008-10-15

申请号：EP97830427.7

申请日：1997-08-27

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Claudio ,  Cassio, Valerio ,  Caprara, Paolo ,  Cereda, Manlio Sergio

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

公开(公告)号：EP1058304B1

公开(公告)日：2005-08-17

申请号：EP99830336.6

申请日：1999-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/60

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76885 ,  H01L2924/3011

公开(公告)号：EP1032035A1

公开(公告)日：2000-08-30

申请号：EP99830100.6

申请日：1999-02-26

Applicant: STMicroelectronics S.r.l. ,  Wafer Scale Integration, Inc.

Inventor： Pozzoni, Pierantonio ,  Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo ,  Irani, Ruston

IPC: H01L21/8247

CPC classification number: H01L27/11521

Abstract: A process for manufacturing electronic semiconductor integrated electronic memory devices having virtual ground and comprising at least a matrix of floating gate memory cells (1), the matrix being formed on a semiconductor substrate (2) with a plurality of continuous bit lines (10) extending across the substrate (2) as discrete parallel strips, comprising at least the following steps:

forming an oxide layer (3) over the matrix region;
depositing the semiconductor throughout with a stack structure which comprises a first conductor layer (4), first dielectric layer (5), and second conductor layer (6);
forming a second dielectric layer (7);
defining floating gate regions (13) by photolithography using a mask of "POLY1 along a first predetermined direction", and associated etching, to define, in said stack structure, a plurality of parallel openings (9);
implanting said parallel openings (9) to confer a predetermined conductivity on the bit line (10) regions;
filling the parallel openings (12) with a photo-sensitive material (11) to protect the matrix bit lines (10).

Abstract translation: 一种用于制造具有虚地电子半导体集成电子存储器设备和包括至少浮动栅极存储器单元的一个矩阵处理（1）中，基体被连续位线的延伸的多个（10）形成在半导体衬底（2） 横跨基片（2）作为离散的平行条带，其包括至少以下步骤：在所述矩阵区域氧化物层（3）上; 沉积半导体整个具有堆叠结构，其包括第一导体层（4），第一电介质层（5）和第二导体层（6）; 形成第二电介质层（7）; 使用的“沿第一预定方向POLY1”掩模，和相关联的蚀刻， - 定义浮置栅极区域（13），通过光刻，以限定在所述堆叠结构，平行的开口（9）的多元性; 注入所述平行的开口（9），以赋予对位线（10）的区域的预定导电性; 填充开口（12）在平行（11）光敏材料，以保护基质的位线（10）。

公开(公告)号：EP1300888A1

公开(公告)日：2003-04-09

申请号：EP01830634.0

申请日：2001-10-08

Applicant: STMicroelectronics S.r.l.

Inventor： Caprara, Paolo ,  Brambilla, Claudio ,  Cereda, Manlio Sergio

IPC: H01L29/792 ,  H01L21/8246 ,  H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  H01L29/7923

Abstract: A process for manufacturing a dual charge storage location electrically programmable memory cell comprises the steps of: forming a central insulated gate ( 12 , 15 ) over a semiconductor substrate ( 11 ); forming physically separated charge-confining layers stack portions of a dielectric-charge trapping material-dielectric layers stack ( 19 , 110 , 111 ; 29 , 210 , 211;49A , B , 410A , B , 411A , B ) at the sides of the central gate, the charge trapping material layer ( 110 ; 210 ; 410A , B ) in each charge-confining layers stack portion forming a charge storage element; forming side control gates ( 113A , B ; 212 ; 312 ; 413A , B ) over each of the charge-confining layers stack portions; forming memory cell source/drain regions ( 115 ; 215 ; 315 ; 415 ) laterally to the side control gates; electrically connecting ( 116 , 117 ; 216 ; 312 ; 416 ) the side control gates to the central gate. Each of the charge-confining layers stack portions at the sides of the central gate is formed with an "L" shape, with a base charge-confining layers stack portion lying on the substrate surface and an upright charge-confining layers stack portion lying against a respective side of the insulated gate.

Abstract translation: 一种用于制造双电荷存储位置电可编程存储器单元的工艺包括以下步骤：在半导体衬底（11）上形成中央绝缘栅极（12,15）; 在中央栅极的侧面处形成物理分离的电荷限制层堆叠电介质电荷俘获材料 - 电介质层堆叠（19,110,111; 29,210,211; 49A，B，410A，B，411A，B）部分，电荷俘获材料层 （110; 210; 410A，B）在每个电荷限制层堆叠部分中形成电荷存储元件; 在每个电荷限制层堆叠部分上方形成侧控制栅极（113A，B; 212; 312; 413A，B） 在所述侧控制栅极的侧面形成存储器单元源极/漏极区域（115; 215; 315; 415） 将所述侧控制栅极电连接到所述中央栅极（116,117; 216; 312; 416）。 中央栅极侧的每个电荷限制层堆叠部分形成为“L”形，其中基础电荷限制层堆叠部分位于衬底表面上，并且竖直电荷限制层堆叠部分抵靠 绝缘栅极的相应侧。

公开(公告)号：EP1032029A1

公开(公告)日：2000-08-30

申请号：EP99830101.4

申请日：1999-02-26

Applicant: STMicroelectronics S.r.l.

Inventor： Cereda, Manlio Sergio ,  Brambilla, Claudio ,  Caprara, Paolo

IPC: H01L21/336 ,  H01L21/8247 ,  H01L21/033

CPC classification number: H01L27/11521 ,  H01L21/0337 ,  H01L29/66825

Abstract: A process for manufacturing electronic semiconductor integrated memory devices having a virtual ground and comprising at least a matrix of floating gate memory cells (1), the matrix being formed on a semiconductor substrate (2) with a plurality of continuous bit lines (BL) extending across the substrate (2) as discrete parallel strips, comprising at least the following steps:

growing an oxide layer (3) over the matrix region;
depositing the semiconductor throughout with a stack structure which comprises a first conductor layer (4), first dielectric layer (5), and second conductor layer (6):
depositing a second dielectric layer (7);
defining floating gate regions (10) by photolithography using a mask of "POLY1 along a first direction", to thereby define, in said dielectric layer (7), a plurality of parallel strips (8) which delimit a first dimension of floating gate regions;
etching away said dielectric layer (7) to define said plurality of parallel dielectric strips (8);
photolithographing by means of a mask of "POLY1 along a second direction" to define a plurality of dielectric islands (9) in said plurality of parallel strips (8);
etching away said dielectric layer (7) to define the plurality of islands (9);
etching away said stack structure (4,5,6) and the thin gate oxide layer (3) to define gate regions (10) of the matrix cells using said oxide island (9).

Abstract translation: 一种用于制造具有一虚拟接地电子半导体集成电路存储器设备和包括至少浮动栅极存储器单元（1）的矩阵处理，该矩阵被连续位线的延伸的多个（BL）形成在半导体衬底（2） 横跨基片（2）作为离散的平行条带，其包括至少以下步骤：氧化物层上生长（3）在所述基体区; 具有堆叠结构，其包括第一导体层（4），第一电介质层（5）和第二导体层沉积在整个半导体（6）上沉积第二电介质层（7）; 使用的掩模“POLY1沿着第一方向”，以由此限定，在所述电介质层（7），一个平行的条带的多元性 - 定义浮置栅极区域（10）通过光刻法（8），该界定浮栅区的第一尺寸 ; 蚀刻掉介电层。所述（7）来定义平行介质带的所述多个（8）; photolithographing通过的“POLY 1沿一第二方向”的掩模手段，以限定电介质岛的多个（9）平行条带（8）在所述多个; 蚀刻掉所述介质层（7）来定义岛屿多个（9）; 蚀刻掉所述叠层结构（4,5,6）以及使用所述基质细胞的薄的栅极氧化物层（3），以限定栅极区（10）氧化物冰岛（9）。

公开(公告)号：EP1017087A1

公开(公告)日：2000-07-05

申请号：EP98830794.8

申请日：1998-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Claudio ,  Cereda, Sergio Manlio ,  Caprara, Paolo

IPC: H01L21/265 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  Y10S438/976

Abstract: A process for manufacturing a MOS transistor (1) integrated in a semiconductor substrate (2) having a first type of conductivity, which process comprises the steps of:

forming a layer (3) of gate oxide over the semiconductor substrate (2);
forming a gate electrode (4) over this oxide layer;
forming a layer (5) of covering oxide over the gate oxide layer (3), the gate electrode (4), and around the gate electrode (4);
implanting a dopant of a second type of conductivity to provide implanted regions (6,6a,6b) adjacent to the gate electrode;
subjecting the semiconductor to thermal treatments to allow the implanted regions (6,6a,6b) to diffuse into the semiconductor substrate (2) under the gate electrode (4) and form gradual junction drain and source regions of said transistor.

Abstract translation: 一种集成在具有第一类导电性的半导体衬底（2）中的MOS晶体管（1）的制造方法，该工艺包括以下步骤：在半导体衬底（2）上形成栅极氧化物层（3）; 在该氧化物层上形成栅电极（4）; 在所述栅极氧化物层（3），所述栅电极（4）和所述栅电极（4）周围形成覆盖氧化物的层（5）。 注入第二类导电性的掺杂剂以提供与栅电极相邻的注入区域（6,6a，6b）; 对半导体进行热处理以允许注入区域（6,6a，6b）扩散到栅极（4）下方的半导体衬底（2）中，并形成所述晶体管的逐渐结的漏极和源极区域。