公开(公告)号：EP1184873B1

公开(公告)日：2008-12-10

申请号：EP00830582.3

申请日：2000-08-16

Applicant: STMicroelectronics S.r.l.

Inventor： Geraci, Antonino ,  Lisi, Carlo ,  Bedarida, Lorenzo ,  Sforzin, Marco

IPC: G11C16/28 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C16/28

公开(公告)号：EP1686591A1

公开(公告)日：2006-08-02

申请号：EP05100551.0

申请日：2005-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Del Gatto, Nicola ,  Ferrario, Marco ,  Confalonieri, Emanuele

IPC: G11C16/26 ,  G11C11/56

CPC classification number: G11C16/26

Abstract: A memory device (100) is proposed. The memory device includes a plurality of memory cells (Mc) each one for storing a value, at least one reference cell (Mr 0 -Mr 2 ), biasing means (115) for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage (Vc,Vr) having a substantially monotone time pattern, means (130) for detecting the reaching of a threshold value by a current (Ic,Ir) of each selected memory cell and of each reference cell, and means (145) for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means (305) for applying a predetermined biasing current (Ib) to the selected memory cells and to the at least one reference cell.

Abstract translation: 一种存储器装置（100）被提议。 所述存储器装置包括存储器单元的用于偏置一组选择的存储单元的多个（MC）每一个用于存储一个值，至少一个参考单元（先生0 -Mr 2），偏压装置（115）和所述至少一个 具有用于每个被选择的存储单元的电流（Ic，Ir）的各基准单元的检测的阈值的到达基本上单调时间图案，装置（130）的偏置电压（VC，VR）参考单元，和 装置（145），用于确定挖掘存储在每个选定存储器单元gemäß阈值的通过和所述至少一个参考单元的选定存储器单元的电流的到达的时间关系的值。 偏压装置包括用于将预定偏置电流（Ib），以所选择的存储器单元和所述至少一个参考蜂窝小区的装置（305）。

公开(公告)号：EP1686591B1

公开(公告)日：2008-01-09

申请号：EP05100551.0

申请日：2005-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Del Gatto, Nicola ,  Ferrario, Marco ,  Confalonieri, Emanuele

IPC: G11C16/26 ,  G11C11/56

CPC classification number: G11C16/26

公开(公告)号：EP1400980A1

公开(公告)日：2004-03-24

申请号：EP02425562.2

申请日：2002-09-17

Applicant: STMicroelectronics S.r.l.

Inventor： Poidomani, Carla ,  Confalonieri, Emanuele ,  Sforzin, Marco ,  Del Gatto, Nicola

IPC: G11C16/24 ,  G11C7/06

CPC classification number: G11C7/062 ,  G11C16/24

Abstract: A circuit (125,130) for biasing an input node (Na) of a sense amplifier (115) is proposed. The circuit includes means (125) for keeping the input node at a pre-set operative voltage during a sensing operation; the circuit of the invention further includes means (250) for pulling the input node from a starting voltage towards a power supply voltage (+Vdd), the operative voltage being comprised between the starting voltage and the power supply voltage, and control means (255) for disabling the means for pulling before the input node reaches the operative voltage.

Abstract translation: 一种用于在读出放大器（115）的输入节点（Na）的偏压电路（125.130）的提议。 该电路包括用于在传感操作保持在预先设定的工作电压的输入节点的装置（125）; 本发明的电路进一步包括：用于从一个起动电压向电源电压（+ VDD），工作电压被包括起始电压和电源电压，和控制装置之间拉动所述输入节点装置（250）（255 ），用于禁止所述用于拉动输入节点达到工作电压之前。

公开(公告)号：EP1221771A1

公开(公告)日：2002-07-10

申请号：EP01830005.3

申请日：2001-01-08

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Bedarida, Lorenzo ,  Defendi, Marco ,  Nava, Claudio

IPC: H03K17/16

CPC classification number: H03K19/00361 ,  H03K17/163

Abstract: The output-buffer circuit (1) comprises an end stage (2) made up of a pull-up transistor (3) and a pull-down transistor (4) connected in series between a supply line (5) and a ground line (GND); a first driving stage (8) connected to a control terminal of the pull-up transistor (3) and comprising a plurality of first driving branches (12) which can be selectively activated by a logic control circuit (16) according to the reading and operating modes of a memory device (100) including the output-buffer circuit (1) and to the variability of the electrical parameters of the output-buffer circuit; and a second driving stage (9) connected to a control terminal of the pull-down transistor (4) and comprising a plurality of second driving branches (22) which can also be selectively activated by the control circuit (16) according to the reading and operating modes of a memory device (100) including the output-buffer circuit (1) and to the variability of the electrical parameters of the output-buffer circuit.

Abstract translation: 输出缓冲电路（1）包括由串联连接在电源线（5）和接地线（5）之间的上拉晶体管（3）和下拉晶体管（4）构成的端级（2） GND）; 第一驱动级（8），连接到所述上拉晶体管（3）的控制端，并且包括多个第一驱动分支（12），所述第一驱动分支可根据所述读取被逻辑控制电路（16）选择性地激活;以及 包括输出缓冲器电路（1）的存储器件（100）的工作模式以及输出缓冲器电路的电气参数的可变性; 以及连接到所述下拉晶体管（4）的控制端子并且包括多个第二驱动分支（22）的第二驱动级（9），所述第二驱动分支（22）还可以根据所述读取被所述控制电路（16）选择性地启动 以及包括输出缓冲器电路（1）的存储器件（100）的工作模式以及输出缓冲器电路的电气参数的变化。

公开(公告)号：EP1646051B1

公开(公告)日：2008-03-05

申请号：EP04425754.1

申请日：2004-10-08

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Del Gatto, Nicola ,  Mollichelli, Massimiliano ,  Scotti, Massimiliano

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C16/30

公开(公告)号：EP1646051A1

公开(公告)日：2006-04-12

申请号：EP04425754.1

申请日：2004-10-08

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Del Gatto, Nicola ,  Mollichelli, Massimiliano ,  Scotti, Massimiliano

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C16/30

Abstract: In a memory device (1; 30) having an array (2) of memory cells (3), a column decoder (9) is configured to address the memory cells (3), and a charge-pump supply circuit (6; 32) generates a boosted supply voltage (V b ; V yr ) for the column decoder (9). A connecting stage (22) is arranged between the supply circuit (6; 32) and the column decoder (9); the connecting stage (22) switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device (1; 30), in particular during a reading step.

Abstract translation: 在存储装置（1; 30），其具有在（2）的存储单元（3）阵列，列解码器（9）被配置为处理存储单元（3），和一个电荷泵电源电路（6; 32 ）生成一个升压电源电压（V b;对列译码器（9）V年）。 和列译码器（9）;所述的连接阶段（22）的供电电路（32 6）之间布置; 连接阶段（22）的高阻抗状态和低阻抗状态之间切换，并且被配置为切换到高阻抗状态的存储装置（1; 30）的给定操作条件的读出期间，尤其是 一步。

公开(公告)号：EP1184873A1

公开(公告)日：2002-03-06

申请号：EP00830582.3

申请日：2000-08-16

Applicant: STMicroelectronics S.r.l.

Inventor： Geraci, Antonino ,  Lisi, Carlo ,  Bedarida, Lorenzo ,  Sforzin, Marco

IPC: G11C16/28 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C16/28

Abstract: A direct-comparison reading circuit for a nonvolatile memory array (2) having a plurality of memory cells (4) arranged in rows and columns (9), and at least one bit line (7), includes at least one array line (13), selectively connectable to the bit line (7), and a reference line (14); a precharging circuit (17) for precharging the array line (13) and reference line (14) at a preset precharging potential (V PC ); at least one comparator (35) having a first terminal connected to the array line (13), and a second terminal connected to the reference line (14); and an equalization circuit (15, 23, 26) for equalizing the potentials of the array line (13) and reference line (14) in the precharging step. In addition, the reading circuit includes an equalization line (15) distinct from the reference line (14); and controlled switches (23, 26) for connecting, in the precharging step, the equalization line (15) to the array line (13) and to the reference line (14), and for disconnecting the equalization line (15) from the array line (13) and from the reference line (14) at the end of the precharging step.

Abstract translation: 一种用于具有以行和列（9）排列的多个存储单元（4）和至少一个位线（7）的非易失性存储器阵列（2）的直接比较读取电路，包括至少一个阵列线（13） ），可选择地连接到位线（7）和参考线（14）; 用于以预设的预充电电位（VPC）对阵列线（13）和参考线（14）进行预充电的预充电电路（17）; 至少一个具有连接到阵列线（13）的第一端子的比较器（35）和连接到参考线（14）的第二端子; 以及用于在预充电步骤中均衡阵列线（13）和参考线（14）的电位的均衡电路（15,23,26）。 另外，读取电路包括与参考线（14）不同的均衡线（15）。 和控制开关（23,26），用于在预充电步骤中将均衡线（15）连接到阵列线（13）和参考线（14），并将均衡线（15）与阵列 在预充电步骤结束时从线（13）和参考线（14）移动。