公开(公告)号：EP1091408A1

公开(公告)日：2001-04-11

申请号：EP99830628.6

申请日：1999-10-07

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo ,  Maurelli, Alfonso ,  Zatelli, Nicola

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

Abstract: The memory cell (101) is of the type with a single level of polysilicon, and comprises a sensing transistor (20) and a select transistor (21). The sensing transistor (20) comprises a control gate region (6) with a second type of conductivity, formed in a first region of active area (30) of a substrate (3) of semiconductor material, and a floating gate region (9) which extends transversely relative to the first region of active area (30). The control gate region (6) of the sensing transistor (20) is surrounded by a first well (103) with the first type of conductivity, and in turn is surrounded, below and laterally, by a second well (104) with the second type of conductivity, thus forming a triple well structure (142). A second triple well structure (140) can be formed in a second region of active area (31) adjacent to the first region of active area (30), and can accommodate conduction regions (4, 5, 12, 14, 15) of the sensing transistor and of the select transistor (21).

Abstract translation: 存储单元（101）是具有单层多晶硅的类型，并且包括感测晶体管（20）和选择晶体管（21）。 感测晶体管（20）包括形成在半导体材料的衬底（3）的有源区域（30）的第一区域中的具有第二类型导电性的控制栅极区域（6）和浮动栅极区域（9） 其相对于有源区域（30）的第一区域横向延伸。 感测晶体管（20）的控制栅极区域（6）由具有第一类型导电性的第一阱（103）围绕，并且又由第二阱（104）包围，在第二阱（104）的下面和侧面，第二阱 导电类型，从而形成三重阱结构（142）。 可以在与有源区域（30）的第一区域相邻的有源区域（31）的第二区域中形成第二三阱结构（140），并且可以适应传导区域（4,5,12,14,15） 感测晶体管和选择晶体管（21）。

公开(公告)号：EP1191601A1

公开(公告)日：2002-03-27

申请号：EP00830628.4

申请日：2000-09-21

Applicant: STMicroelectronics S.r.l.

Inventor： Zatelli, Nicola ,  Atti, Massimo ,  Palumbo, Elisabetta ,  Torelli, Cosimo

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/417

CPC classification number: H01L29/41725 ,  H01L29/7835

Abstract: A lateral DMOS transistor having a drain region (13, 14) which comprises a high-concentration portion (14) with which the drain electrode (D) is in contact and a low-concentration portion (13) which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode (25) in contact with a point of the low-concentration portion of the drain region (13, 14) which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.

Abstract translation: 一种具有漏极区域（13,14）的横向DMOS晶体管，包括漏电极（D）与其接触的高浓度部分（14）和由沟道区域限定的低浓度部分（13） 。 除了传统的源极，漏极，主体和栅极之外，晶体管具有与漏极区域（13,14）的靠近沟道的低浓度部分的点接触的附加电极（25）。 附加电极允许直接测量栅极电介质中的电场，并且因此提供可用于表征晶体管并选择其尺寸的信息，并且用于激活用于保护晶体管和/或其中包含的集成电路的其它部件的器件 晶体管。

公开(公告)号：EP1191601B1

公开(公告)日：2007-11-28

申请号：EP00830628.4

申请日：2000-09-21

Applicant: STMicroelectronics S.r.l.

Inventor： Zatelli, Nicola ,  Atti, Massimo ,  Palumbo, Elisabetta ,  Torelli, Cosimo

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/417

CPC classification number: H01L29/41725 ,  H01L29/7835

公开(公告)号：EP1109217A1

公开(公告)日：2001-06-20

申请号：EP99830770.6

申请日：1999-12-13

Applicant: STMicroelectronics S.r.l.

Inventor： Palumbo, Elisabetta ,  Peschiaroli, Daniela ,  Zatelli, Nicola

IPC: H01L21/8239 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11546

Abstract: The body regions for the n-channel and p-channel LV transistors, for the n-channel HV transistors, and for the EPROM cells are formed on a silicon substrate; a thermal oxide layer (12) is formed and a layer of polycrystalline silicon (13) is formed thereon; the latter layer is selectively removed to form the floating gate electrodes (13a) of the cells and the gate electrodes (13b) of the HV transistors; the source and drain regions (14) of the cells, the source and drain regions (22) of the n-channel HV transistors, the body regions (24) and the source and drain regions of the p-channel HV transistors are formed; an ONO composite layer (15) is formed; the silicon of the areas of the LV transistors is exposed; a thermal oxide layer (16) is formed on the exposed areas; a second polycrystalline silicon layer (17) is deposited and is then removed selectively to form the gate electrodes of the LV transistors (17c) and the control gate electrodes (17a) of the cells, and the source and drain regions of the LV transistors are formed.
By virtue of the use of a material (ONO) which is impermeable to the oxygen atoms of the subsequent thermal oxidation and because the body regions (24) of the p-channel HV transistors and the source and drain regions of all of the HV transistors are produced by separate implantations, components of very good quality are produced with few more masks than a conventional LV method.

Abstract translation: 用于n沟道HV晶体管的n沟道和p沟道LV晶体管的主体区域和用于EPROM单元的体区域形成在硅衬底上; 形成热氧化物层（12），并在其上形成多晶硅层（13）; 选择性地去除后一层以形成单元的浮置栅电极（13a）和HV晶体管的栅电极（13b）; 形成单元的源极和漏极区域（14），n沟道HV晶体管的源极和漏极区域（22），体区域（24）以及p沟道HV晶体管的源极和漏极区域; 形成ONO复合层（15）; 暴露出LV晶体管的区域的硅; 在暴露的区域上形成热氧化层（16）; 沉积第二多晶硅层（17），然后选择性地去除以形成单元的LV晶体管（17c）和控制栅电极（17a）的栅电极，并且LV晶体管的源极和漏极区域 形成。 由于使用对随后的热氧化的氧原子不可渗透的材料（ONO），并且由于p沟道HV晶体管的体区（24）和所有HV晶体管的源极和漏极区域 通过单独的注入产生，非常好质量的组分以比常规LV方法少得多的掩模产生。

公开(公告)号：EP1132959A1

公开(公告)日：2001-09-12

申请号：EP00830162.4

申请日：2000-03-03

Applicant: STMicroelectronics S.r.l.

Inventor： Atti, Massimo ,  Maurelli, Alfonso ,  Zatelli, Nicola

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/8246

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: The method applies to non-volatile semiconductor memories with cells arranged in rows and in columns, in which each cell has a first terminal (CG), a second terminal (D), and a third terminal (S) connected, respectively, to a row line (WLi), to a column line (BLi), and to a common node by respective connection strips (CG, R). In order to form connections with low resistivity and consequently to save semiconductor area, the method provides for the formation of an oxide layer (I2) which covers the connection strips of the first terminals (CG) and of the third terminals (S), the formation of channels (CH1, CH2) along the connection strips until the surfaces thereof are exposed, and the filling of the channels (CH1, CH2) with a material (W) having a resistivity lower than that of the connection strips.

Abstract translation: 该方法适用于具有排列成行和列的单元的非易失性半导体存储器，其中每个单元具有分别连接到第一端子（CG），第二端子（D）和第三端子（S）的单元 行线（WLi）到列线（BLi），并且通过相应的连接条（CG，R）连接到公共节点。 为了形成具有低电阻率的连接并因此节省半导体面积，该方法提供了覆盖第一端子（CG）和第三端子（S）的连接条的氧化物层（I2）的形成， 沿着连接条形成通道（CH1，CH2），直到其表面露出，并且用具有低于连接条的电阻率的材料（W）填充通道（CH1，CH2）。

公开(公告)号：EP1096575A1

公开(公告)日：2001-05-02

申请号：EP99830629.4

申请日：1999-10-07

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo ,  Maurelli, Alfonso ,  Zatelli, Nicola

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

Abstract: The memory cell (101) is of the type with a single level of polysilicon, and is produced in a substrate (102) of semiconductor material with a first type of conductivity, and comprises a control gate region (6) with a second type of conductivity, formed in the substrate (102) in a first region of active area (30); regions of source (4a, 4b) and drain (5a, 5b) with the second type of conductivity, formed in the substrate (102) in a second region of active area (31); and a floating gate region (9) which extends transversely relative to the first (30) and the second (31) regions of active area. The control gate region (6) is surrounded by a first well (103) with the first type of conductivity, which in turn is surrounded, below and laterally, by a third well (108) with the second type of conductivity. The regions of source (4a, 4b) and drain (5a, 5b) are accommodated in a second well (104) with the first type of conductivity, which in turn is surrounded below and laterally by a fourth well (112) with the second type of conductivity.

Abstract translation: 存储单元（101）是具有单层多晶硅的类型，并且在具有第一类导电性的半导体材料的衬底（102）中制造，并且包括具有第二类型的多晶硅的控制栅极区域（6） 导电性，形成在有源区域（30）的第一区域中的衬底（102）中; 源极（4a，4b）和具有第二类型导电性的漏极（5a，5b）的区域在有源区域（31）的第二区域中形成在衬底（102）中。 以及相对于有效区域的第一（30）和第二（31）区域横向延伸的浮动栅极区域（9）。 控制栅极区域（6）由具有第一类型导电性的第一阱（103）包围，第一阱具有第二类型的导电性，第三阱又由具有第二类型导电性的第三阱（108）包围。 源极（4a，4b）和漏极（5a，5b）的区域被容纳在具有第一类型导电性的第二阱（104）中，第二阱导电性又被第四阱（112）包围并在第二阱 导电类型。

公开(公告)号：EP1104022A1

公开(公告)日：2001-05-30

申请号：EP99830742.5

申请日：1999-11-29

Applicant: STMicroelectronics S.r.l.

Inventor： Crivelli, Barbera ,  Peschiaroli, Daniela ,  Palumbo, Elisabetta ,  Zatelli, Nicola

IPC: H01L21/8239 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11539 ,  Y10S438/981

Abstract: The active areas and the body regions for the LV MOS transistors, for the HV MOS transistors and for the EPROM cells are formed on a silicon substrate, a layer of thermal oxide is formed, and a layer of polycrystalline silicon is formed on it, the last-mentioned layer is removed selectively to form the floating gate electrodes (13a) of the cells, the source and drain regions of the cells are formed, the silicon of the areas of the HV MOS transistors is exposed, a layer of HTO oxide is formed and nitrided, the silicon of the areas of the LV MOS transistors is exposed, a layer of thermal oxide (16) is formed on the exposed areas, a second layer of polycrystalline silicon is deposited and is then removed selectively to form the gate electrodes of the LV and HV MOS transistors (17c, 17b) and the control gate electrodes (17a) of the cells, and the source and drain regions of the LV and HV MOS transistors are formed. Owing to the simultaneous formation of the gate dielectric of the HV MOS transistors and the intermediate dielectric of the cells, and the use of a material (nitrided HTO oxide) which is impermeable to the oxygen atoms of the subsequent thermal oxidation, the number of the operations in the process is smaller than in the prior art process.

Abstract translation: 有源区和用于LV MOS晶体管的体区，用于HV MOS晶体管和用于EPROM细胞在一个硅衬底上形成时，热氧化物的层被形成，和多晶硅层形成在其上，所述 最后提到的层被选择性地移除以形成所述单元的浮置栅电极（13A），该单元的源区和漏区上形成时，HV MOS晶体管的区域中的硅被暴露，HTO氧化物层是 形成，并且氮化中，LV MOS晶体管的区域中的硅被暴露，热氧化层（16）形成在暴露区域，多晶硅的第二层被沉积，然后除去有选择地形成栅电极 LV和HV MOS晶体管（17C，17B）和所述单元的控制栅电极（17A），和LV和HV MOS晶体管的源区和漏区的形成。 由于HV MOS晶体管的栅极电介质和细胞的中间电介质，以及使用的材料（氮化HTO氧化物）的所有不透随后的热氧化的氧原子，的数的同时形成 在这个过程中的操作比现有技术的方法要小。

公开(公告)号：EP1104021A1

公开(公告)日：2001-05-30

申请号：EP99830741.7

申请日：1999-11-29

Applicant: STMicroelectronics S.r.l.

Inventor： Palumbo, Elisabetta ,  Peschiaroli, Daniela ,  Zatelli, Nicola

IPC: H01L21/8239 ,  H01L21/8247

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11546

Abstract: The active areas and the body regions for the LV MOS transistors, for the HV MOS transistors and for the EPROM cells are formed on a silicon substrate, a layer of thermal oxide (12) is formed and a layer of polycrystalline silicon (13) is formed on it, the last-mentioned layer is removed selectively to form the floating gate electrodes (13a) of the cells, the source and drain regions (14) of the cells are formed, a composite ONO layer (15) is formed, the silicon of the areas of the LV MOS transistors is exposed, a layer of thermal oxide (16) is formed on the exposed areas, a second layer of polycrystalline silicon (17) is deposited and is then removed selectively to form the gate electrodes of the LV and HV MOS transistors (17c, 17b) and the control gate electrodes (17a) of the cells, and the source and drain regions of the LV and HV MOS transistors are formed.
Owing to the simultaneous formation of part of the gate dielectric of the HV MOS transistors and the intermediate dielectric of the cells, and the use of a material (ONO) which is impermeable to the oxygen atoms of the subsequent thermal oxidation, the number of the operations in the process is smaller than in the prior art process.

Abstract translation: 有源区和用于LV MOS晶体管的体区，用于HV MOS晶体管和用于EPROM单元形成在硅衬底上，热氧化层（12）被形成和多晶硅（13）的层是 在其上形成，最后提到的层被选择性地去除，以形成细胞的细胞，所述源和漏区（14）的浮栅电极（13A）的部分，复合ONO层（15）形成，所述 所述LV MOS晶体管的区域的硅被暴露，热氧化层（16）形成在暴露区域，多晶硅的第二层（17）被沉积，然后除去有选择地形成的栅极电极 LV和HV MOS晶体管（17C，17B）和所述单元的控制栅电极（17A），和LV和HV MOS晶体管的源极和漏极区域形成。 由于同时形成的HV MOS晶体管的栅极电介质和细胞的中间电介质，以及使用的材料（ONO）的组成部分的所有不透随后的热氧化的氧原子，的数 在这个过程中的操作比现有技术的方法要小。

公开(公告)号：EP0926686A1

公开(公告)日：1999-06-30

申请号：EP97830697.5

申请日：1997-12-23

Applicant: STMicroelectronics S.r.l.

Inventor： Zatelli, Nicola

IPC: G11C16/04

CPC classification number: G11C16/0416

Abstract: The non-volatile memory comprises a MOS selection transistor (40) having an input terminal (41) receiving a first voltage (V IN ), an output terminal (42) supplying a second voltage (V OUT ), a control terminal (43) receiving a third voltage (V G ) and a bulk region (52) housing conductive regions (53, 54) connected to the input and output terminals. The selection transistor (40) is a P-channel transistor and the bulk region (52) is biased at a fourth voltage (V B ) not less than the first voltage (V IN ).

Abstract translation: 非易失性存储器包括：MOS选择晶体管（40），其具有接收第一电压（VIN）的输入端（41），提供第二电压（VOUT）的输出端（42），接收第 第三电压（VG）和容纳连接到输入和输出端子的导电区域（53,54）的整体区域（52）。 选择晶体管（40）是P沟道晶体管，并且体区（52）被以不小于第一电压（VIN）的第四电压（VB）偏置。