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公开(公告)号：US20100231768A1
公开(公告)日：2010-09-16
申请号：US12722121
申请日：2010-03-11
Applicant: Hiroto Utsunomiya , Katsumi Dosaka , Hiroshi Kato , Fukashi Morishita , Fumiyasu Sasaki
Inventor： Hiroto Utsunomiya , Katsumi Dosaka , Hiroshi Kato , Fukashi Morishita , Fumiyasu Sasaki
IPC: H04N5/335
CPC classification number: H04N5/37455 , H03M1/1205 , H03M1/144 , H03M1/403 , H03M1/66 , H03M2201/16 , H04N5/374 , H04N5/3742 , H04N5/3765 , H04N5/378
Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.
Abstract translation: 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。
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公开(公告)号：US3935569A
公开(公告)日：1976-01-27
申请号：US397924
申请日：1973-09-17
Applicant: Francois Marcel , Alain Manoury
Inventor： Francois Marcel , Alain Manoury
IPC: H03M1/14 , H03M1/00 , H03K13/175
CPC classification number: H03M1/00 , H03M2201/01 , H03M2201/14 , H03M2201/16 , H03M2201/196 , H03M2201/2208 , H03M2201/3115 , H03M2201/3131 , H03M2201/4105 , H03M2201/4135 , H03M2201/4204 , H03M2201/4225 , H03M2201/4233 , H03M2201/4262 , H03M2201/52 , H03M2201/522 , H03M2201/523 , H03M2201/534 , H03M2201/60 , H03M2201/6121
Abstract: The invention concerns a digital coder subject to a compression law having multiple linear segments with slopes decreasing in geometrical progression having a ratio of 1/2, in which a chain of threshold detectors in a linear progression is used a first time to determine the number of the segment, then a second time to determine the position of the level on the segment.
Abstract translation: 本发明涉及经受压缩规律的数字编码器，该数字编码器具有多个线性段，其斜率以1/2的比例在几何级数上减小，其中使用线性进程中的阈值检测器链第一次来确定 该段，然后第二次确定段上的水平位置。
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公开(公告)号：US20160212367A1
公开(公告)日：2016-07-21
申请号：US15082913
申请日：2016-03-28
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Hiroto UTSUNOMIYA , Katsumi DOSAKA , Hiroshi KATO , Fukashi MORISHITA , Fumiyasu SASAKI
IPC: H04N5/3745 , H04N5/376 , H03M1/66 , H04N5/378
CPC classification number: H04N5/37455 , H03M1/1205 , H03M1/144 , H03M1/403 , H03M1/66 , H03M2201/16 , H04N5/374 , H04N5/3742 , H04N5/3765 , H04N5/378
Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.
Abstract translation: 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。
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公开(公告)号：US09300892B2
公开(公告)日：2016-03-29
申请号：US14256680
申请日：2014-04-18
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Hiroto Utsunomiya , Katsumi Dosaka , Hiroshi Kato , Fukashi Morishita , Fumiyasu Sasaki
CPC classification number: H04N5/37455 , H03M1/1205 , H03M1/144 , H03M1/403 , H03M1/66 , H03M2201/16 , H04N5/374 , H04N5/3742 , H04N5/3765 , H04N5/378
Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.
Abstract translation: 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。
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5.发明授权Transmitter for forming non-linear pulse code modulated samples of analog signals by timing the integral of signal samples 失效用于形成模拟信号的非线性脉冲代码调制样本的发送器通过定时信号样本的整合
公开(公告)号：US4010422A
公开(公告)日：1977-03-01
申请号：US409425
申请日：1973-10-25
Applicant: Kornelis Jan Wouda
Inventor： Kornelis Jan Wouda
CPC classification number: H04B14/04 , H03M1/00 , H04B14/048 , H03M2201/01 , H03M2201/14 , H03M2201/16 , H03M2201/196 , H03M2201/2344 , H03M2201/4105 , H03M2201/4135 , H03M2201/4204 , H03M2201/4212 , H03M2201/4225 , H03M2201/4233 , H03M2201/425 , H03M2201/4262 , H03M2201/52 , H03M2201/523 , H03M2201/534 , H03M2201/60 , H03M2201/6121 , H03M2201/712 , H03M2201/715 , H03M2201/8124
Abstract: A non-linear pulse code modulator wherein input signals are coded into digital representations of amplitude range segments and amplitude in excess of the minimum amplitude within the respective range segment uses a first analog-to-digital converter having a sawtooth-shaped control characteristic to determine the amplitude range segment from an input signal sample. The output of the first analog-to-digital converter is used to effectively divide the signal sample by a factor 2.sup.n, where n corresponds to the determined range. The result of the division is then converted in a second analog-to-digital conversion to a digital signal that is combined with the digital range segment signal for transmission thereof.
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Patent Agency Ranking
公开(公告)号：US09560300B2
公开(公告)日：2017-01-31
申请号：US15082913
申请日：2016-03-28
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Hiroto Utsunomiya , Katsumi Dosaka , Hiroshi Kato , Fukashi Morishita , Fumiyasu Sasaki
CPC classification number: H04N5/37455 , H03M1/1205 , H03M1/144 , H03M1/403 , H03M1/66 , H03M2201/16 , H04N5/374 , H04N5/3742 , H04N5/3765 , H04N5/378
Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.
Abstract translation: 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。
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公开(公告)号：US20140226049A1
公开(公告)日：2014-08-14
申请号：US14256680
申请日：2014-04-18
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Hiroto UTSUNOMIYA , Katsumi DOSAKA , Hiroshi KATO , Fukashi MORISHITA , Fumiyasu SASAKI
IPC: H04N5/369
CPC classification number: H04N5/37455 , H03M1/1205 , H03M1/144 , H03M1/403 , H03M1/66 , H03M2201/16 , H04N5/374 , H04N5/3742 , H04N5/3765 , H04N5/378
Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.
Abstract translation: 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。
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公开(公告)号：US08736732B2
公开(公告)日：2014-05-27
申请号：US12722121
申请日：2010-03-11
Applicant: Hiroto Utsunomiya , Katsumi Dosaka , Hiroshi Kato , Fukashi Morishita , Fumiyasu Sasaki
Inventor： Hiroto Utsunomiya , Katsumi Dosaka , Hiroshi Kato , Fukashi Morishita , Fumiyasu Sasaki
IPC: H04N5/335
CPC classification number: H04N5/37455 , H03M1/1205 , H03M1/144 , H03M1/403 , H03M1/66 , H03M2201/16 , H04N5/374 , H04N5/3742 , H04N5/3765 , H04N5/378
Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.
Abstract translation: 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。
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9.发明授权Amplifier for analogue signal samples with automatic gain control, and circuit for digitisation of such samples 失效具有自动增益控制的模拟信号样本的放大器，以及这些样本的数字化电路
公开(公告)号：US3936819A
公开(公告)日：1976-02-03
申请号：US322333
申请日：1973-01-10
Applicant: Philippe Angelle , Georges Lefevre
Inventor： Philippe Angelle , Georges Lefevre
CPC classification number: H03M1/00 , G11C27/026 , H03F3/72 , H03M2201/01 , H03M2201/14 , H03M2201/16 , H03M2201/2241 , H03M2201/2283 , H03M2201/4105 , H03M2201/4135 , H03M2201/4204 , H03M2201/4212 , H03M2201/4233 , H03M2201/4262 , H03M2201/534 , H03M2201/712 , H03M2201/715 , H03M2201/8124
Abstract: An electronic device for amplifying, with automatic gain control by discr values, analogue signal samples and thereafter preferably effecting analogue-to-digital conversion of the samples, consists of an amplifier circuit, a comparator circuit, and a delay store circuit. The amplifier has a basic gain during a gain control or gain ranging operation, and supplies an output sample amplified with sufficient gain to bring it into the region of a predetermined voltage. The comparator circuit compares the output of the amplifier circuit with a reference and supplies an output in accordance with the result of the comparison. For analogue-to-digital conversion the amplifier circuit supplies for an input signal U an output signal 2U - VQ, where VQ is the quantification voltage, or, in other embodiments a signal 2U.
Abstract translation: 用于通过离散值的自动增益控制来放大模拟信号样本的电子装置，其后优选地进行样本的模数转换，由放大器电路，比较器电路和延迟存储电路组成。 放大器在增益控制或增益测距操作期间具有基本增益，并且以足够的增益提供放大的输出样本，使其进入预定电压的区域。 比较器电路将放大器电路的输出与参考值进行比较，并根据比较结果提供输出。 对于模拟到数字转换，放大器电路为输入信号U提供输出信号2U-VQ，其中VQ是量化电压，或者在其它实施例中为信号2U。
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公开(公告)号：JP5332041B2
公开(公告)日：2013-11-06
申请号：JP2009205918
申请日：2009-09-07
Applicant: ルネサスエレクトロニクス株式会社
CPC classification number: H04N5/37455 , H03M1/1205 , H03M1/144 , H03M1/403 , H03M1/66 , H03M2201/16 , H04N5/374 , H04N5/3742 , H04N5/3765 , H04N5/378
Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.
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