公开(公告)号：US3936819A

公开(公告)日：1976-02-03

申请号：US322333

申请日：1973-01-10

Applicant: Philippe Angelle ,  Georges Lefevre

Inventor： Philippe Angelle ,  Georges Lefevre

IPC: H03M1/40 ,  G11C27/02 ,  H03F3/72 ,  H03G3/20 ,  H03M1/00 ,  H03K13/02

CPC classification number: H03M1/00 ,  G11C27/026 ,  H03F3/72 ,  H03M2201/01 ,  H03M2201/14 ,  H03M2201/16 ,  H03M2201/2241 ,  H03M2201/2283 ,  H03M2201/4105 ,  H03M2201/4135 ,  H03M2201/4204 ,  H03M2201/4212 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/534 ,  H03M2201/712 ,  H03M2201/715 ,  H03M2201/8124

Abstract: An electronic device for amplifying, with automatic gain control by discr values, analogue signal samples and thereafter preferably effecting analogue-to-digital conversion of the samples, consists of an amplifier circuit, a comparator circuit, and a delay store circuit. The amplifier has a basic gain during a gain control or gain ranging operation, and supplies an output sample amplified with sufficient gain to bring it into the region of a predetermined voltage. The comparator circuit compares the output of the amplifier circuit with a reference and supplies an output in accordance with the result of the comparison. For analogue-to-digital conversion the amplifier circuit supplies for an input signal U an output signal 2U - VQ, where VQ is the quantification voltage, or, in other embodiments a signal 2U.

Abstract translation: 用于通过离散值的自动增益控制来放大模拟信号样本的电子装置，其后优选地进行样本的模数转换，由放大器电路，比较器电路和延迟存储电路组成。 放大器在增益控制或增益测距操作期间具有基本增益，并且以足够的增益提供放大的输出样本，使其进入预定电压的区域。 比较器电路将放大器电路的输出与参考值进行比较，并根据比较结果提供输出。 对于模拟到数字转换，放大器电路为输入信号U提供输出信号2U-VQ，其中VQ是量化电压，或者在其它实施例中为信号2U。

公开(公告)号：US4010422A

公开(公告)日：1977-03-01

申请号：US409425

申请日：1973-10-25

Applicant: Kornelis Jan Wouda

Inventor： Kornelis Jan Wouda

IPC: H03M1/00 ,  H04B14/04 ,  H04B1/04

CPC classification number: H04B14/04 ,  H03M1/00 ,  H04B14/048 ,  H03M2201/01 ,  H03M2201/14 ,  H03M2201/16 ,  H03M2201/196 ,  H03M2201/2344 ,  H03M2201/4105 ,  H03M2201/4135 ,  H03M2201/4204 ,  H03M2201/4212 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/425 ,  H03M2201/4262 ,  H03M2201/52 ,  H03M2201/523 ,  H03M2201/534 ,  H03M2201/60 ,  H03M2201/6121 ,  H03M2201/712 ,  H03M2201/715 ,  H03M2201/8124

Abstract: A non-linear pulse code modulator wherein input signals are coded into digital representations of amplitude range segments and amplitude in excess of the minimum amplitude within the respective range segment uses a first analog-to-digital converter having a sawtooth-shaped control characteristic to determine the amplitude range segment from an input signal sample. The output of the first analog-to-digital converter is used to effectively divide the signal sample by a factor 2.sup.n, where n corresponds to the determined range. The result of the division is then converted in a second analog-to-digital conversion to a digital signal that is combined with the digital range segment signal for transmission thereof.

公开(公告)号：US4626827A

公开(公告)日：1986-12-02

申请号：US475405

申请日：1983-03-15

Applicant: Masatsugu Kitamura ,  Mitsuaki Tanaka ,  Hiroyuki Takekura

Inventor： Masatsugu Kitamura ,  Mitsuaki Tanaka ,  Hiroyuki Takekura

IPC: H03M1/00 ,  H04B14/04 ,  H03K13/02

CPC classification number: H03M1/00 ,  H04B14/046 ,  H03M2201/02 ,  H03M2201/162 ,  H03M2201/196 ,  H03M2201/198 ,  H03M2201/20 ,  H03M2201/3115 ,  H03M2201/4105 ,  H03M2201/4135 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/531 ,  H03M2201/532 ,  H03M2201/534 ,  H03M2201/535 ,  H03M2201/648 ,  H03M2201/712 ,  H03M2201/715 ,  H03M2201/8128 ,  H03M2201/834

Abstract: A data compression system comprises an analog-to-digital converter for quantizing the analog signal at a first sampling frequency into a series of digital samples and a memory for storing the digital samples. A control circuit generates a sampling datum indicating a variable sampling frequency lower than the first sampling frequency as a function of the instantaneous frequency of the analog signal for selecting digital samples from the memory, reads the selected digital samples out of the memory means in response to the sampling datum, and forms the sampling datum and the selected digital samples into a data set. A series of data sets may be transmitted to a receiving end of the system or stored in a recording medium. The sampling datum is used to indicate the point at which the digital sample is converted to a corresponding analog value.

Abstract translation: 数据压缩系统包括用于将第一采样频率的模拟信号量化成一系列数字样本的模数转换器和用于存储数字样本的存储器。 控制电路根据用于从存储器中选择数字样本的模拟信号的瞬时频率的函数产生指示低于第一采样频率的可变采样频率的采样数据，以响应于从存储器装置读出所选择的数字样本 采样数据，并将采样数据和所选择的数字样本组成数据集。 一系列数据集可以传送到系统的接收端或存储在记录介质中。 采样数据用于指示数字采样转换为相应模拟值的点。

公开(公告)号：US4568912A

公开(公告)日：1986-02-04

申请号：US475406

申请日：1983-03-15

Applicant: Masatsugu Kitamura ,  Mitsuaki Tanaka

Inventor： Masatsugu Kitamura ,  Mitsuaki Tanaka

IPC: H03M1/00 ,  H04B12/02

CPC classification number: H03M1/00 ,  H03M2201/02 ,  H03M2201/162 ,  H03M2201/196 ,  H03M2201/198 ,  H03M2201/3115 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/415 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/532 ,  H03M2201/534 ,  H03M2201/648 ,  H03M2201/838

Abstract: In a data compression system, a digital signal comprising a series of digital samples and a sampling datum associated with each digital sample is received by a decoder. The sampling datum indicates the sampling interval of the associated digital sample. The decoder includes a microcomputer for storing the digital signal into a memory (M2) and reading each digital sample and the associated sampling datum. The digital sample is divided by the sampling datum to derive a quotient which indicates the slope of the signal to be recovered. The quotient is integrated by an integrator (6b) to provide interpolation between successive sampling points, so that the original signal is approximated by a plurality of line segments.

Abstract translation: 在数据压缩系统中，由解码器接收包括一系列数字样本和与每个数字样本相关联的采样数据的数字信号。 采样数据表示相关数字采样的采样间隔。 解码器包括用于将数字信号存储到存储器（M2）中并读取每个数字样本和相关联的采样数据的微型计算机。 数字样本被采样数据除以导出指示要恢复的信号的斜率的商。 积分器（6b）对商进行积分，以在连续采样点之间提供内插，使原始信号由多个线段近似。

公开(公告)号：US3935569A

公开(公告)日：1976-01-27

申请号：US397924

申请日：1973-09-17

Applicant: Francois Marcel ,  Alain Manoury

Inventor： Francois Marcel ,  Alain Manoury

IPC: H03M1/14 ,  H03M1/00 ,  H03K13/175

CPC classification number: H03M1/00 ,  H03M2201/01 ,  H03M2201/14 ,  H03M2201/16 ,  H03M2201/196 ,  H03M2201/2208 ,  H03M2201/3115 ,  H03M2201/3131 ,  H03M2201/4105 ,  H03M2201/4135 ,  H03M2201/4204 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/52 ,  H03M2201/522 ,  H03M2201/523 ,  H03M2201/534 ,  H03M2201/60 ,  H03M2201/6121

Abstract: The invention concerns a digital coder subject to a compression law having multiple linear segments with slopes decreasing in geometrical progression having a ratio of 1/2, in which a chain of threshold detectors in a linear progression is used a first time to determine the number of the segment, then a second time to determine the position of the level on the segment.

Abstract translation: 本发明涉及经受压缩规律的数字编码器，该数字编码器具有多个线性段，其斜率以1/2的比例在几何级数上减小，其中使用线性进程中的阈值检测器链第一次来确定 该段，然后第二次确定段上的水平位置。

公开(公告)号：KR1020060109397A

公开(公告)日：2006-10-20

申请号：KR1020060094476

申请日：2006-09-28

Applicant: 이종우

Inventor： 이종우

IPC: H03M1/00 ,  G06F7/00

CPC classification number: H03M1/1235 ,  G06F7/00 ,  H03M1/002 ,  H03M1/14 ,  H03M2201/196 ,  H03M2201/534 ,  H03M2201/76

Abstract: A pipeline analog to digital converter to implement a logarithmic function is provided to introduce a pipeline structure for performing a conversion by a relatively fixed reference voltage without influence of a device characteristic or an environment. A method for implementing a pipeline analog to digital converter to implement a logarithmic function includes the steps of: implementing an analog digital converter by using a basic mathematical relation of the logarithmic function; calculating an amplification ratio of a differential amplifier and a reference voltage formula; constituting a circuit by only a scalar product without using a product function circuit; constructing a dependent circuit of 1.5 bit structure; calculating final 8 bit data by calculating the generated 1.5 bit digital signal; dividing into two stages to correct the large amplification ratio at the first stage; and correcting errors by measuring a polarity determined through the comparator before a sample/hold circuit again.

Abstract translation: 提供了一种用于实现对数函数的管线模数转换器，用于引入用于通过相对固定的参考电压执行转换的流水线结构，而不受设备特性或环境的影响。 一种用于实现流水线模数转换器以实现对数函数的方法包括以下步骤：通过使用对数函数的基本数学关系实现模拟数字转换器; 计算差分放大器的放大比和参考电压公式; 仅使用标量产品构成电路，而不使用产品功能电路; 构建1.5比特结构的依赖电路; 通过计算生成的1.5位数字信号计算最终的8位数据; 分为两个阶段，以纠正第一阶段的大放大率; 并且通过在再次采样/保持电路之前测量通过比较器确定的极性来校正误差。