公开(公告)号：US4350976A

公开(公告)日：1982-09-21

申请号：US215134

申请日：1980-12-10

Applicant: Roger Benoit-Gonin ,  Jean L. Berger ,  Jean L. Coutures

Inventor： Roger Benoit-Gonin ,  Jean L. Berger ,  Jean L. Coutures

IPC: H03M1/66 ,  H03M1/00 ,  H03K13/02

CPC classification number: H03M1/00 ,  H03M2201/02 ,  H03M2201/2241 ,  H03M2201/2266 ,  H03M2201/2291 ,  H03M2201/3105 ,  H03M2201/3178 ,  H03M2201/4135 ,  H03M2201/4212 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/81 ,  H03M2201/8128 ,  H03M2201/814 ,  H03M2201/837

Abstract: Successive two-trip traversals of charges between gates G.sub.0 and G.sub.2 make it possible to obtain beneath gates G.sub.1 and G.sub.2 quantities of charges equal to Q.sub.R, Q.sub.R /2, Q.sub.R /2.sup.2 . . . Q.sub.R /2.sup.i. A readout device for reading charges and connected to gates G.sub.2 and G.sub.4 generates voltages V.sub.R and V.sub.Ri =a.sub.0 .multidot.V.sub.R +a.sub.1 .multidot.V.sub.R /2+ . . . +a.sub.i-1 .multidot.V.sub.R /2.sup.i-1 +V.sub.R /2.sup.i which are compared with a voltage sample V.sub.x to be coded in order to determine by successive approximations the coefficients a.sub.0 . . . a.sub.n which are equal to 0 or to 1 such that V.sub.x =a.sub.0 .multidot.V.sub.R +a.sub.1 .multidot.V.sub.R /2+ . . . +a.sub.n .multidot.V.sub.R /2.sup.n. Depending on the value of a.sub.i, each quantity of charges Q.sub.R /2.sup.i stored beneath gate G.sub.1 is removed beneath diode D.sub.e or stored beneath gate G.sub.3 and then transferred beneath gate G.sub.4.

Abstract translation: 栅极G0和G2之间的电荷的连续两次跳变使得可以获得栅极G1和G2之下的等于QR，QR / 2，QR / 22的电荷量。 。 。 QR / 2i 用于读取电荷并连接到门G2和G4的读出装置产生电压VR和VRi = a0xVR + a1xVR / 2 +。 。 。 + ai-1xVR / 2i-1 + VR / 2i，其与要编码的电压采样Vx进行比较，以便通过逐次逼近来确定系数a0。 。 。 a等于0或1，使得Vx = a0xVR + a1xVR / 2 +。 。 。 + anxVR / 2n。 根据ai的值，存储在栅极G1下方的每个电荷量QR / 2i在二极管De下方被去除或存储在栅极G3下方，然后在栅极G4下方传送。

公开(公告)号：US3936819A

公开(公告)日：1976-02-03

申请号：US322333

申请日：1973-01-10

Applicant: Philippe Angelle ,  Georges Lefevre

Inventor： Philippe Angelle ,  Georges Lefevre

IPC: H03M1/40 ,  G11C27/02 ,  H03F3/72 ,  H03G3/20 ,  H03M1/00 ,  H03K13/02

CPC classification number: H03M1/00 ,  G11C27/026 ,  H03F3/72 ,  H03M2201/01 ,  H03M2201/14 ,  H03M2201/16 ,  H03M2201/2241 ,  H03M2201/2283 ,  H03M2201/4105 ,  H03M2201/4135 ,  H03M2201/4204 ,  H03M2201/4212 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/534 ,  H03M2201/712 ,  H03M2201/715 ,  H03M2201/8124

Abstract: An electronic device for amplifying, with automatic gain control by discr values, analogue signal samples and thereafter preferably effecting analogue-to-digital conversion of the samples, consists of an amplifier circuit, a comparator circuit, and a delay store circuit. The amplifier has a basic gain during a gain control or gain ranging operation, and supplies an output sample amplified with sufficient gain to bring it into the region of a predetermined voltage. The comparator circuit compares the output of the amplifier circuit with a reference and supplies an output in accordance with the result of the comparison. For analogue-to-digital conversion the amplifier circuit supplies for an input signal U an output signal 2U - VQ, where VQ is the quantification voltage, or, in other embodiments a signal 2U.

Abstract translation: 用于通过离散值的自动增益控制来放大模拟信号样本的电子装置，其后优选地进行样本的模数转换，由放大器电路，比较器电路和延迟存储电路组成。 放大器在增益控制或增益测距操作期间具有基本增益，并且以足够的增益提供放大的输出样本，使其进入预定电压的区域。 比较器电路将放大器电路的输出与参考值进行比较，并根据比较结果提供输出。 对于模拟到数字转换，放大器电路为输入信号U提供输出信号2U-VQ，其中VQ是量化电压，或者在其它实施例中为信号2U。

公开(公告)号：KR1020110042730A

公开(公告)日：2011-04-27

申请号：KR1020090099536

申请日：2009-10-20

Applicant: 인하대학교 산학협력단

Inventor： 윤광섭 ,  김원

IPC: H03M1/12

CPC classification number: H03M1/362 ,  H03M1/1205 ,  H03M1/14 ,  H03M2201/196 ,  H03M2201/2216 ,  H03M2201/2241

Abstract: PURPOSE: An analog to digital converter using partial encoding is provided to eliminate the asynchronous problem between codes due to a bottleneck phenomenon. CONSTITUTION: A voltage distributing unit(100) distributes a reference voltage. A range detector unit(200) generates a control signal. A first frontal amplifying unit(300) amplifies two differential reference voltages and two differential analog signals. A second frontal amplifying unit(400) amplifies two output signals from the first frontal amplifying unit. A comparison unit(700) synchronizes two amplification signals of a frontal amplifier of the second frontal amplifying unit. A switch unit(800) is switched on/off based on four control signals. An upper encoder unit encodes two upper bits of six bits. A lower encoder unit encodes four lower bits of six bits. A synchronization unit(1100) synchronizes the output signals of the upper encoder unit and the lower encoder unit according to a main clock signal.

Abstract translation: 目的：提供使用部分编码的模数转换器，以消除由于瓶颈现象引起的代码间的异步问题。 构成：电压分配单元（100）分配参考电压。 距离检测器单元（200）产生控制信号。 第一正面放大单元（300）放大两个差分参考电压和两个差分模拟信号。 第二正面放大单元（400）放大来自第一正面放大单元的两个输出信号。 比较单元（700）同步第二正面放大单元的正面放大器的两个放大信号。 基于四个控制信号，开关单元（800）被接通/断开。 上编码器单元编码6位的两位高位。 较低的编码器单元编码六位的四位低位。 同步单元（1100）根据主时钟信号同步上编码器单元和下编码器单元的输出信号。