公开(公告)号：US4350976A

公开(公告)日：1982-09-21

申请号：US215134

申请日：1980-12-10

Applicant: Roger Benoit-Gonin ,  Jean L. Berger ,  Jean L. Coutures

Inventor： Roger Benoit-Gonin ,  Jean L. Berger ,  Jean L. Coutures

IPC: H03M1/66 ,  H03M1/00 ,  H03K13/02

CPC classification number: H03M1/00 ,  H03M2201/02 ,  H03M2201/2241 ,  H03M2201/2266 ,  H03M2201/2291 ,  H03M2201/3105 ,  H03M2201/3178 ,  H03M2201/4135 ,  H03M2201/4212 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/81 ,  H03M2201/8128 ,  H03M2201/814 ,  H03M2201/837

Abstract: Successive two-trip traversals of charges between gates G.sub.0 and G.sub.2 make it possible to obtain beneath gates G.sub.1 and G.sub.2 quantities of charges equal to Q.sub.R, Q.sub.R /2, Q.sub.R /2.sup.2 . . . Q.sub.R /2.sup.i. A readout device for reading charges and connected to gates G.sub.2 and G.sub.4 generates voltages V.sub.R and V.sub.Ri =a.sub.0 .multidot.V.sub.R +a.sub.1 .multidot.V.sub.R /2+ . . . +a.sub.i-1 .multidot.V.sub.R /2.sup.i-1 +V.sub.R /2.sup.i which are compared with a voltage sample V.sub.x to be coded in order to determine by successive approximations the coefficients a.sub.0 . . . a.sub.n which are equal to 0 or to 1 such that V.sub.x =a.sub.0 .multidot.V.sub.R +a.sub.1 .multidot.V.sub.R /2+ . . . +a.sub.n .multidot.V.sub.R /2.sup.n. Depending on the value of a.sub.i, each quantity of charges Q.sub.R /2.sup.i stored beneath gate G.sub.1 is removed beneath diode D.sub.e or stored beneath gate G.sub.3 and then transferred beneath gate G.sub.4.

Abstract translation: 栅极G0和G2之间的电荷的连续两次跳变使得可以获得栅极G1和G2之下的等于QR，QR / 2，QR / 22的电荷量。 。 。 QR / 2i 用于读取电荷并连接到门G2和G4的读出装置产生电压VR和VRi = a0xVR + a1xVR / 2 +。 。 。 + ai-1xVR / 2i-1 + VR / 2i，其与要编码的电压采样Vx进行比较，以便通过逐次逼近来确定系数a0。 。 。 a等于0或1，使得Vx = a0xVR + a1xVR / 2 +。 。 。 + anxVR / 2n。 根据ai的值，存储在栅极G1下方的每个电荷量QR / 2i在二极管De下方被去除或存储在栅极G3下方，然后在栅极G4下方传送。

公开(公告)号：KR101132216B1

公开(公告)日：2012-04-02

申请号：KR20100121962

申请日：2010-12-02

Applicant: KUMOH NAT INST TECH ACAD COOP

Inventor： UH JI HUN ,  JANG YOUNG CHAN

IPC: H03M1/12

CPC classification number: H03M1/0617 ,  H03M1/802 ,  H03M3/02 ,  H03M2201/3178 ,  H03M2201/6142

Abstract: PURPOSE: A digital to analog converter with a routing dummy capacitor is provided to improve the resolution of a digital to analog converter by reducing analog noise generated from a switch of an output terminal in the digital-to-analog converter. CONSTITUTION: A first positive polarity DAC(Digital To Analog Converter) part(210) comprises a plurality of first positive polarity switches(211a, 211e) and a plurality of unit capacitors(212a, 212e). A second positive polarity DAC part(220) comprises a plurality of second positive polarity switches(221a, 212e) and a plurality of unit capacitors(222a, 222e). A first negative polarity DAC part(230) comprises a plurality of first negative polarity switches(231a,231e) and a plurality of unit capacitors(232a,232e). The second negative polarity DAC part(240) comprises a plurality of second negative polarity switches(241a,241e) and a plurality of unit capacitors(242a,242e). A positive polarity capacitor(250) is connected between the first positive polarity DAC part and the second positive polarity DAC part. A negative polarity capacitor(260) is connected between the first negative polarity DAC part and the second negative polarity DAC part.

Abstract translation: 目的：提供具有路由虚拟电容器的数模转换器，以通过减少由数模转换器中的输出端子的开关产生的模拟噪声来提高数模转换器的分辨率。 构成：第一正极性DAC（数模转换器）部分（210）包括多个第一正极性开关（211a，211e）和多个单位电容器（212a，212e）。 第二正极性DAC部分（220）包括多个第二正极性开关（221a，212e）和多个单位电容器（222a，222e）。 第一负极性DAC部分（230）包括多个第一负极性开关（231a，231e）和多个单位电容器（232a，232e）。 第二负极性DAC部分（240）包括多个第二负极性开关（241a，241e）和多个单位电容器（242a，242e）。 正极性电容器（250）连接在第一正极性DAC部分和第二正极性DAC部分之间。 负极性电容器（260）连接在第一负极性DAC部分和第二负极性DAC部分之间。

公开(公告)号：KR1020090022980A

公开(公告)日：2009-03-04

申请号：KR1020070098091

申请日：2007-09-28

Applicant: 한국전자통신연구원 ,  한양대학교 산학협력단

Inventor： 권오경 ,  김창선 ,  차진종 ,  윤병진

IPC: H03M1/12

CPC classification number: H03M1/0621 ,  H03M1/002 ,  H03M1/802 ,  H03M2201/2233 ,  H03M2201/2291 ,  H03M2201/3178 ,  H03M2201/64

Abstract: A digital-analog converter and an analog-digital converter using the same are provided to obtain an accurate data conversion result by removing the influence of the parasitic capacitance through a virtual ground. A digital-analog converter(1000) includes a first type capacitor array(320) and a second type capacitor array(340), and a charge re-distributor(360). The first and second type capacitor arrays have the different array configuration. The charge re-distributor resets the charge in response to the digital data set in the first and second type capacitor arrays. The charge re-distributor generates the analog voltage corresponding to the electric charge reset result. The first type capacitor array is a weighted capacitor array. The second type capacitor array is a charge sharing capacitor array.

Abstract translation: 提供数模转换器和使用该数模转换器的模数转换器，以通过去除虚拟接地的寄生电容的影响来获得精确的数据转换结果。 数模转换器（1000）包括第一类型电容器阵列（320）和第二类型电容器阵列（340）和电荷再分配器（360）。 第一和第二类型电容器阵列具有不同的阵列配置。 电荷再分配器响应于第一和第二类型电容器阵列中的数字数据而重置电荷。 充电重新分配器产生对应于电荷复位结果的模拟电压。 第一类电容器阵列是加权电容阵列。 第二类电容器阵列是电荷共享电容阵列。