公开(公告)号：US10039185B2

公开(公告)日：2018-07-31

申请号：US15130724

申请日：2016-04-15

Applicant: Kinsus Interconnect Technology Corp.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H01K3/10 ,  H05K1/11 ,  H05K3/18 ,  H05K3/42 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K1/115 ,  H05K1/113 ,  H05K3/0047 ,  H05K3/0079 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/18 ,  H05K3/429 ,  H05K3/4644 ,  H05K3/4647 ,  H05K2203/054 ,  Y10T29/49165

Abstract: Provided is a landless multilayer circuit board and a manufacturing method thereof. The manufacturing method includes steps of forming a first circuit on a first substrate, patterning a photoresist layer to form at least one via between the first circuit and a second circuit, forming at least one connecting pillar in the at least one via, removing the photoresist layer, forming a second substrate to cover the at least one connect pillar, and forming the second circuit on the second substrate. The second circuit is connected to the first circuit through the at least one connecting pillar. When the second circuit is formed, the at least one via does not need to be filled, thereby making the second circuit flat.

公开(公告)号：US20180132351A1

公开(公告)日：2018-05-10

申请号：US15863605

申请日：2018-01-05

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H05K1/09 ,  H05K1/14 ,  H05K1/02

CPC classification number: H05K1/09 ,  H05K1/0298 ,  H05K1/144 ,  H05K3/4614 ,  H05K2201/0367 ,  H05K2201/042 ,  H05K2201/09472

Abstract: A multi-layer circuit board includes a first circuit board, conducting blocks, a second circuit board, and conducting recesses. The first circuit board has a first conductor layer mounted on the first circuit board. The conducting blocks are mounted on the first circuit board and electrically connected to the first conductor layer. The second circuit board has a second conductor layer mounted thereon and facing the first circuit board. The conducting recesses are formed in the second circuit board, electrically connected to the second conductor layer, and corresponding to the respective conducting blocks. The insulating layer is mounted between the first conductor layer and the second conductor layer. The second circuit board is on the first circuit board, the conducting blocks are respectively mounted in the conducting recesses to electrically connect the first conductor layer and the second conductor layer.

公开(公告)号：US09901016B1

公开(公告)日：2018-02-20

申请号：US15488133

申请日：2017-04-14

Applicant: Kinsus Interconnect Technology Corp.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yung-Lin Chia

IPC: H05K9/00

CPC classification number: H05K9/0037 ,  H05K9/003

Abstract: An EMI shielding device is provided. A first shielding layer is formed on a first surface of a first substrate, and a first through hole is formed through the first substrate. A second substrate is mounted in an opening of the first through hole, and a second shielding layer is formed on a surface of the second substrate. A conductive paste is mounted between the first substrate and the at least one second substrate to electrically connected the first shielding layer and the second shielding layer. A protective layer, an antirust layer, and a shielding layer are sequentially mounted on the conductive paste. The EMI shielding device is mounted on a printed circuit board (PCB) by Surface Mount Technology. Therefore, the EMI shielding device may be firmly mounted on the PCB, and there is not any narrow gap that may leak electromagnetic radiation.

公开(公告)号：US20170318671A1

公开(公告)日：2017-11-02

申请号：US15143354

申请日：2016-04-29

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H05K1/09 ,  H05K1/02

CPC classification number: H05K1/09 ,  H05K1/0298 ,  H05K1/144 ,  H05K3/4614 ,  H05K2201/0367 ,  H05K2201/042 ,  H05K2201/09472

Abstract: A multi-layer circuit board includes a first circuit board, multiple conducting blocks, a second circuit board, and multiple conducting recesses. The first circuit board has a first conductor layer formed thereon. The conducting blocks are mounted on the first circuit board and electrically connected to the first conductor layer. The second circuit board has a second conductor layer mounted thereon and facing the first circuit board. The conducting recesses are formed in the surface of the second circuit board. Each conducting recess has a conducting layer electrically connected to the second conductor layer. When the conducting blocks are mounted in the conducting recesses, the first conductor layer and the second conductor layer are electrically connected through the conducting blocks and the conducting recesses. As can be separated from the first circuit board for test of the two conductor layers, the yield of the second circuit board is enhanced.

公开(公告)号：US20170311443A1

公开(公告)日：2017-10-26

申请号：US15138261

申请日：2016-04-26

Applicant: Kinsus Interconnect Technology Corp.

Inventor： Ting-Hao LIN ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H05K1/02 ,  H05K3/10 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/42 ,  H05K1/0284 ,  H05K1/0296 ,  H05K1/112 ,  H05K3/007 ,  H05K3/4647 ,  H05K2201/0376 ,  H05K2203/0733 ,  H05K2203/1476 ,  Y10T29/49165

Abstract: Provided is a double layer circuit board and a manufacturing method thereof. The double layer circuit board comprises a substrate, a first circuit layer formed on a first surface of the substrate, a second circuit layer formed on a second surface of the substrate, and at least one connecting pillar formed in and covered by the substrate. Each one of the at least one connecting pillar includes a first end connected to the first circuit layer and a second end connected to the second circuit layer. A terminal area of the second end is greater than a terminal area of the first end. Therefore, the second circuit layer is firmly connected to the first circuit layer through the at least one connecting pillar. A yield rate of the double layer circuit board may be increased.

公开(公告)号：US20170287617A1

公开(公告)日：2017-10-05

申请号：US15086333

申请日：2016-03-31

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H01F27/28 ,  H01F27/06 ,  H05K3/46 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01F27/2804 ,  H01F2027/2809 ,  H05K1/0393 ,  H05K1/113 ,  H05K1/118 ,  H05K1/165 ,  H05K3/4617 ,  H05K3/4644

Abstract: A buildup board structure incorporating magnetic induction coils and flexible boards is disclosed. The buildup board structure includes at least one first, second and third buildup bodies modular and stackable. Any two adjacent buildup bodies are separated by a covering layer provided with a central hole for electrical insulation. All central holes are aligned. Each buildup body includes a plurality of flexible boards, and each flexible board is embedded with a plurality of magnetic induction coils surrounding the corresponding central hole and connected through connection pads. The first, second and third buildup bodies are easily laminated in any order by any number as desired such that the effect of magnetic induction provided by the magnetic induction coils embedded in the buildup board structure are addable to greatly enhance the overall effect of magnetic induction.

公开(公告)号：US20170103844A1

公开(公告)日：2017-04-13

申请号：US14877981

申请日：2015-10-08

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H01F27/28 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F41/041 ,  H01F2027/2809 ,  H05K1/00 ,  H05K1/165 ,  H05K3/00 ,  H05K3/4635 ,  H05K2201/09063

Abstract: A winged coil structure and a method of manufacturing the same are disclosed. The winged coil structure includes an upper flexible plate, at least one upper magnetic induction coil, at least one upper connection pad, a lower flexible plate, at least one lower magnetic induction coil, at least one lower connection pad, at least one gold finger, a dielectric layer and at least one connection plug. The connection plug connects the upper connection pad and the lower connection pad through thermal pressing such that the gold finger, the upper magnetic induction coil, the upper connection pad, the lower connection pad, the connection plug, the lower connection pad and the lower magnetic induction coil are electrically connected. The upper flexible plate is provided with notched lines to be easily bent without damage to the upper and lower magnetic induction coils. Thus, a bendable feature for magnetic induction coils is provided.

公开(公告)号：US20160374206A1

公开(公告)日：2016-12-22

申请号：US14742070

申请日：2015-06-17

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Jaen-Don Lan ,  PIN-CHUNG LIN ,  CHEN-RUI TSENG ,  CHENG-EN HO ,  YU-AN CHEN

IPC: H05K3/00 ,  B23K26/402 ,  H05K3/16 ,  B23K26/386

CPC classification number: B23K26/402 ,  B23K26/382 ,  B23K26/389 ,  B23K2101/40 ,  B23K2103/172 ,  B23K2103/30 ,  B23K2103/42 ,  B23K2103/50 ,  H05K3/426 ,  H05K3/4644 ,  H05K2201/0341

Abstract: Disclosed is a method for manufacturing a circuit board, including preparing a substrate having a resin layer and a stop layer, forming at least one conduction hole penetrating the resin layer and stopping at the stop layer, forming a first metal layer through a sputtering process, forming a second metal layer on the first metal layer through a chemical plating process, forming a third metal layer having a circuit pattern, exposing part of the second metal layer and filling up the conduction hole through an electroplating process, and etching the second metal layer and the first metal layer under the second metal layer to expose the resin layer under the first metal layer. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and stable. The etched circuit pattern has a line width/pitch less than 10 μm for fine line width/pitch.

Abstract translation: 公开了一种制造电路板的方法，包括制备具有树脂层和停止层的基板，形成穿过树脂层的至少一个导电孔并在停止层处停止，通过溅射工艺形成第一金属层， 通过化学镀工艺在第一金属层上形成第二金属层，形成具有电路图案的第三金属层，暴露第二金属层的一部分并通过电镀工艺填充导电孔，并蚀刻第二金属层 以及第二金属层下面的第一金属层，以暴露第一金属层下的树脂层。 由于第一金属层提供优异的表面性质，所以第二和第三金属层是良好固定和稳定的。 蚀刻电路图案对于细线宽/间距具有小于10μm的线宽/间距。

公开(公告)号：US20160372409A1

公开(公告)日：2016-12-22

申请号：US14742098

申请日：2015-06-17

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Jaen-Don Lan ,  PIN-CHUNG LIN ,  CHEN-RUI TSENG ,  CHENG-EN HO ,  YU-AN CHEN

IPC: H01L23/498

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894

Abstract: Disclosed is a circuit board structure, including the first, second and third metal layers sequentially stacked on the substrate from bottom to top and formed by the sputtering process, the chemical plating process and the electroplating process, respectively. The substrate includes the stop layer and the resin layer stacked on the stop layer. The stop layer includes a pattern having at least one contact region, which is not covered by the resin layer. The first, second and third metal layers have an etched circuit pattern, respectively, and each of the etched circuit patterns is provided out of the corresponding contact region and aligned to each other to expose part of the resin layer. The etched circuit pattern is used for electrical connection. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and more stable.

Abstract translation: 公开了一种电路板结构，其包括分别从底部到顶部依次层叠在基板上的第一，第二和第三金属层，并通过溅射工艺，化学镀工艺和电镀工艺形成。 基板包括停止层和层叠在停止层上的树脂层。 止挡层包括具有至少一个不被树脂层覆盖的接触区域的图案。 第一，第二和第三金属层分别具有蚀刻电路图案，并且每个蚀刻电路图案被提供在相应的接触区域之外并且彼此对准以暴露部分树脂层。 蚀刻电路图案用于电连接。 由于第一金属层提供优异的表面性质，所以第二和第三金属层是良好固定的并且更稳定。

公开(公告)号：US20160262267A1

公开(公告)日：2016-09-08

申请号：US14641016

申请日：2015-03-06

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yi-Fan Kao ,  Jaen-Don Lan ,  Yung-Lin Chia ,  An-Ping Tseng

IPC: H05K3/06 ,  H05K3/00 ,  H05K1/18

CPC classification number: H05K3/064 ,  H01L23/5389 ,  H05K1/185 ,  H05K1/188 ,  H05K3/0008 ,  H05K3/108 ,  H05K3/305 ,  H05K3/425 ,  H05K2201/09563 ,  H05K2201/10674 ,  H05K2203/166

Abstract: A method for manufacturing a circuit board with a buried element having high density pin count, wherein a micro copper window formed in a first circuit by patterned dry film electroplating is easily controlled less than 50 μm so that the micro conduction holes formed after the laser drilling each has a diameter greatly shrunk less than 50 μm so as to highly increase density of the micro conduction holes, thereby facilitating in burial of the buried element with the high density pin count. Additionally, by disposing the micro conduction holes in the same elevation, optically aligning a fixing position for the buried element can be controlled precisely.

Abstract translation: 一种制造具有高密度引脚数的埋入元件的电路板的方法，其中通过图案化干电镀电镀形成在第一电路中的微铜窗容易控制在小于50μm，从而在激光钻孔之后形成的微导电孔 每个具有大大缩小到小于50μm的直径，从而高度增加微通孔的密度，从而便于以高密度引脚数掩埋埋入元件。 此外，通过将相同高度的微通孔设置在一起，可精确地控制掩埋元件的固定位置的光学对准。