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公开(公告)号：KR1020020045494A
公开(公告)日：2002-06-19
申请号：KR1020010036933
申请日：2001-06-27
Applicant: 삼성전자주식회사
IPC: H01L21/283
Abstract: PURPOSE: A method for forming a semiconductor device having low permittivity interlayer dielectric is provided to exactly form a micro pattern on a SiOC layer and to restrain a parasitic capacitance between interconnections or contact plugs by using the SiOC layer having a low dielectric constant. CONSTITUTION: A low permittivity carbon oxide silicon layer made of SiOC is formed on a substrate(100) by a CVD(Chemical Vapour Deposition) using a nitrogen included gas as a source gas or a carrier gas. A plasma processing is performed on the carbon oxide silicon layer by supplying gases, such as a helium, a hydrogen, an N2O, or an Ar gas to a processing chamber. A photoresist is deposited and patterned on the plasma processed carbon oxide silicon layer(111).
Abstract translation: 目的：提供一种形成具有低介电常数层间电介质的半导体器件的方法，以在SiOC层上精确地形成微图案，并通过使用具有低介电常数的SiOC层来抑制互连或接触插塞之间的寄生电容。 构成：使用含氮气体作为原料气体或载气，通过CVD（化学气相沉积）在基板（100）上形成由SiOC制成的低介电常数碳氧化硅层。 通过向处理室供给诸如氦气，氢气，N 2 O或Ar气体的气体，对碳氧化硅硅层进行等离子体处理。 在等离子体处理的碳氧化硅层（111）上沉积并图案化光致抗蚀剂。
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公开(公告)号：KR1020020012106A
公开(公告)日：2002-02-15
申请号：KR1020000070973
申请日：2000-11-27
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A method for manufacturing an interconnection using a hydrogen silsesquioxane(HSQ) layer as an interlayer dielectric is provided to simplify a process for forming the interconnection, by performing a plasma treatment regarding the HSQ layer so that the HSQ layer is not damaged in a photolithography process to directly pattern the HSQ layer. CONSTITUTION: A low dielectric layer is formed on a semiconductor substrate(10). A plasma treatment process is performed regarding the entire surface of the low dielectric layer. The plasma-treated low dielectric layer is patterned to form an opening exposing a predetermined region of the semiconductor substrate. A conductive layer filling the opening is formed on the entire surface of the semiconductor substrate.
Abstract translation: 目的：提供一种使用氢倍半硅氧烷（HSQ）层作为层间电介质制造互连的方法，以简化形成互连的工艺，通过对HSQ层进行等离子体处理，使得HSQ层在 光刻工艺直接对HSQ层进行图案化。 构成：在半导体衬底（10）上形成低介电层。 对低介电层的整个表面进行等离子体处理。 将等离子体处理的低介电层图案化以形成暴露半导体衬底的预定区域的开口。 填充开口的导电层形成在半导体衬底的整个表面上。
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公开(公告)号：KR100311047B1
公开(公告)日：2001-11-05
申请号：KR1019990052390
申请日：1999-11-24
Applicant: 삼성전자주식회사
Inventor： 신홍재
IPC: H01L21/3205
Abstract: 본발명의반도체소자의구리배선층은하지층상에형성되고표면근방에제1 트랜치가형성된제1 층간절연막과, 상기제1 트랜치를매립하는제1 구리배선층과, 상기제1 구리배선층상에순차적으로형성된식각정지패턴및 알루미늄필라를포함한다. 그리고, 상기알루미늄필라의양측벽에는형성되지않고상기제1 구리배선층상에만형성된확산및 산화방지막과, 상기확산및 산화방지막과알루미늄필라상에형성되고상기알루미늄필라의상부를노출하는제2 트랜치가형성된제2 층간절연막과, 상기제2 트랜치를매립하는제2 구리배선층을포함한다. 상기확산및 산화방지막은증착과식각이인시츄로진행되는고밀도플라즈마화학기상증착법(HDP CVD)을이용하여형성될수 있다. 이상의본 발명의반도체소자는확산및 산화방지막이알루미늄필라들사이에남아있지않아알루미늄필라들사이에존재하는커패시터의커패시턴스값을감소시켜 RC 지연시간을줄일수 있다.
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公开(公告)号：KR1020010081501A
公开(公告)日：2001-08-29
申请号：KR1020000007120
申请日：2000-02-15
Applicant: 삼성전자주식회사
IPC: H01L29/786
Abstract: PURPOSE: A manufacturing method of a semiconductor device is to prevent generation of a void when depositing an interlayer dielectric for burying a space between gates, thereby improving reliability of the device. CONSTITUTION: Gate patterns(26,28,30) are formed on a semiconductor substrate(22) including a cell array region and a peripheral circuit region therein. Impurities for a source/drain is implanted into the substrate and an etch stop layer(32) is formed on the resultant structure. The first spacer is formed on sidewalls of the gate pattern on the peripheral circuit region. Impurities for an LDD(lightly doped drain) is implanted into the substrate, followed by removing the first spacer. The first interlayer dielectric(38) is then formed such that spaces between the gate patterns are buried and upper portions thereof are exposed. The second spacer(40') is then formed on the exposed sidewalls of each gate pattern, and the second interlayer dielectric(42) is formed thereon to bury completely the space between the gate patterns. Thereafter, a conductive layer(44) is formed to be connected with an active region through the first and second interlayer dielectrics.
Abstract translation: 目的：半导体器件的制造方法是为了防止在沉积用于掩埋栅极之间的空间的层间电介质时产生空隙，从而提高器件的可靠性。 构成：栅极图案（26,28,30）形成在其中包括单元阵列区域和外围电路区域的半导体衬底（22）上。 源极/漏极的杂质被注入到衬底中，并且在所得结构上形成蚀刻停止层（32）。 第一间隔物形成在外围电路区域上的栅极图案的侧壁上。 将LDD（轻掺杂漏极）的杂质注入到衬底中，然后除去第一间隔物。 然后形成第一层间电介质（38），使得掩模栅极图案之间的空间和其上部被暴露。 然后在每个栅极图案的暴露的侧壁上形成第二间隔物（40'），并且在其上形成第二层间电介质（42），以完全掩埋栅极图案之间的空间。 此后，形成通过第一和第二层间电介质与有源区连接的导电层（44）。
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公开(公告)号：KR100292409B1
公开(公告)日：2001-06-01
申请号：KR1019990018663
申请日：1999-05-24
Applicant: 삼성전자주식회사
IPC: H01L21/31
CPC classification number: H01L23/53295 , C04B35/5603 , C04B35/565 , H01L21/02137 , H01L21/0214 , H01L21/02282 , H01L21/02332 , H01L21/0234 , H01L21/02362 , H01L21/3122 , H01L21/76801 , H01L21/76826 , H01L21/76829 , H01L21/76835 , H01L23/5222 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , Y10T428/24843 , Y10T428/24926 , Y10T428/263 , Y10T428/31663 , H01L2924/00
Abstract: Si-CH결합을함유하는절연층의접착특성을향상시킨다층구조의절연막및 그형성방법에관하여개시한다. 본발명에따른다층구조의절연막은도전패턴위에형성되고, 그내부에 Si-CH결합을함유하는저유전막으로이루어지는제1 절연층을포함한다. 상기제1 절연층의접착특성을향상시키기위하여, 상기제1 절연층을플라즈마처리하여상기제1 절연층표면에접착면을형성하거나, 상기제1 절연층표면에버퍼층을형성함으로써, 절연층들사이에다이폴-다이폴상호작용 (dipole-dipole interaction)이이루어질수 있도록한다.
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Patent Agency Ranking
公开(公告)号：KR1020010010171A
公开(公告)日：2001-02-05
申请号：KR1019990028908
申请日：1999-07-16
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A method for forming a dual damascene wiring is provided to make a dual damascene wiring having a fine line width, by forming a topology having a small step difference on a semiconductor substrate after filling inorganic SOG layer in a via contact hole. CONSTITUTION: A first insulation layer pattern for defining a via contact hole is formed on a semiconductor substrate. Inorganic SOG layer fills the via contact hole so as to expose an upper surface of the first insulation layer pattern. A second insulation layer pattern for defining a wiring area(42) is formed on the first insulation layer pattern. The inorganic SOG layer for filling the via contact hole is etched and removed. A conductive material fills the exposed via contact hole and the exposed wiring area, thereby making a dual damascene wiring.
Abstract translation: 目的：提供一种用于形成双镶嵌布线的方法，通过在通孔接触孔中填充无机SOG层之后，在半导体基板上形成具有小阶梯差的拓扑结构，形成具有细线宽度的双镶嵌布线。 构成：在半导体衬底上形成用于限定通孔接触孔的第一绝缘层图案。 无机SOG层填充通孔接触孔，以露出第一绝缘层图案的上表面。 用于限定布线区域（42）的第二绝缘层图案形成在第一绝缘层图案上。 蚀刻并除去用于填充通孔接触孔的无机SOG层。 导电材料通过接触孔和暴露的布线区填充暴露的通孔，从而形成双镶嵌布线。
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公开(公告)号：KR100278657B1
公开(公告)日：2001-02-01
申请号：KR1019980023920
申请日：1998-06-24
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: 반도체 장치의 금속 배선 구조 및 그 제조 방법을 개시한다. 본 발명의 일 관점은, 반도체 기판 상에 형성된 금속막 패턴과, 금속막 패턴을 절연시키는 절연막 및 계면 보호막 등으로 구비된다. 절연막은 실리콘 산화 불화물(SiOF) 등과 같은 불소 원소를 함유하는 절연물 등으로 형성된다. 계면 보호막은 절연막 및 상기 금속막 패턴의 계면에서 알루미늄 산화막, 실리콘 질화막 또는 실리콘 산화 질화막 등으로 형성되어 절연막으로부터 금속막 패턴을 보호한다.
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公开(公告)号：KR1020000054889A
公开(公告)日：2000-09-05
申请号：KR1019990003227
申请日：1999-02-01
Applicant: 삼성전자주식회사
Abstract: PURPOSE: A semiconductor device with an air gap is to provide a stable structure when highly integrated, to avoid a RC delay problem, and to increase a signal transmitting speed. CONSTITUTION: A semiconductor device comprises an interlayer insulation layer(5) having a via hole(11) on a semiconductor substrate(1) on which a lower conductive layer(3) is formed, the via hole exposing the lower conductive layer, and an air gap(13) adjacent to the via hole; an anti-etching layer(7) formed on the interlayer insulation layer; a liner layer(9) formed on both sides of the via hole; a barrier metallic layer(15) formed on a bottom of the via hole, on the anti-etching layer, and on the liner layer; and an upper conductive layer formed on the barrier metallic layer as to bury the via hole, the interlayered layer being a SOG(spin on glass), and the liner layer being an oxidation layer.
Abstract translation: 目的：具有气隙的半导体器件是在高度集成时提供稳定的结构，以避免RC延迟问题，并增加信号传输速度。 构成：半导体器件包括在其上形成有下导电层（3）的半导体衬底（1）上具有通孔（11）的层间绝缘层（5），暴露下导电层的通孔和 邻近通孔的气隙（13）; 形成在所述层间绝缘层上的抗蚀刻层（7） 形成在所述通孔的两侧的衬垫层（9） 在所述通孔的底部，所述防蚀刻层上和所述衬垫层上形成的阻挡金属层（15） 以及在阻挡金属层上形成的用于埋置通孔的上导电层，所述层间层为SOG（玻璃上旋涂），所述衬垫层为氧化层。
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公开(公告)号：KR1020000040530A
公开(公告)日：2000-07-05
申请号：KR1019980056190
申请日：1998-12-18
Applicant: 삼성전자주식회사
IPC: H01L21/31
Abstract: PURPOSE: A method of forming an interlayer insulating film is to form a void on an insulating film between conductive patterns, lowering a dielectric constant of the insulating film, to thereby decrease the capacitance of a parasitic capacitor. CONSTITUTION: A method of forming an interlayer insulating film comprises the steps of: forming a first conductive layer pattern(42) on a substrate(40); forming on the substrate an interlayer insulating film covering the first conductive layer pattern, such that a portion having a lower dielectric constant than that of a surrounding interlayer insulating film is formed on the interlayer insulating film between the first conductive layer pattern; planarizing a whole surface of the interlayer insulating film; forming on the planarized interlayer insulating film a via hole(54) exposing the first conductive layer film; and forming on the interlayer insulating film a second conductive layer pattern(58) connecting with the first conductive layer pattern.
Abstract translation: 目的：形成层间绝缘膜的方法是在导电图案之间的绝缘膜上形成空隙，降低绝缘膜的介电常数，从而降低寄生电容器的电容。 构成：形成层间绝缘膜的方法包括以下步骤：在衬底（40）上形成第一导电层图案（42）; 在所述基板上形成覆盖所述第一导电层图案的层间绝缘膜，使得在所述第一导电层图案之间的所述层间绝缘膜上形成介电常数低于周围层间绝缘膜的介电常数的部分; 平面化层间绝缘膜的整个表面; 在平坦化的层间绝缘膜上形成暴露第一导电层膜的通孔（54）; 以及在所述层间绝缘膜上形成与所述第一导电层图案连接的第二导电层图案（58）。
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公开(公告)号：KR1019990081299A
公开(公告)日：1999-11-15
申请号：KR1019980015148
申请日：1998-04-28
Applicant: 삼성전자주식회사
IPC: H01L21/31
Abstract: 층간절연막 형성방법에 관해 개시되어 있다. 패턴간의 간격이 넓은 곳에 먼저 증착과 식각이 인-시츄로 동시에 진행되는 HDP-CVD막을 소정의 두께로 형성한 다음, 이 위에 저유전율의 SOG막을 도포한 후 베이크한다. 이 결과, 기생 정전용량이 낮을 뿐만 아니라 후속 공정에 대해 크랙 저항도 높은 SOG막을 얻을 수 있다.
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