Abstract:
본 발명은 반도체 기술에 관한 것으로, 특히 제조 공정과 특성 제어가 용이한 전력 집적회로(Integrated Circuit, IC)에 관한 것이며, 그 불순물 확산 영역 형성이 용이하여, 소자의 특성을 용이하게 제어할 수 있는 구조를 가진 전력 집적회로를 제공하는데 그 목적이 있다. 본 발명은 SOI(Silicon-On-Insulator) 기판의 활성 실리콘층에 제공되는 제1 도전형-LDMOS(Lateral Double-diffused Metal Oxide Semiconductor) 트랜지스터, 제2 도전형-LDMOS 트랜지스터 및 CMOS(Complementary Metal Oxide Semiconductor) 트랜지스터를 구비한 전력 집적회로에 있어서, 상기 제1 도전형-LDMOS 트랜지스터가 상기 활성 실리콘층 내의 깊은 제2 도전형 웰에 RESURF(REduced-SURface Field)형으로 제공되며, 상기 제2 도전형-LDMOS 트랜지스터가 상기 활성 실리콘층 내의 깊은 제2 도전형 웰에 비-RESURF형으로 제공되는 것을 특징으로 한다.
Abstract:
본 발명은 다중 게이트 모스(MOS) 트랜지스터 및 그 제조 방법에 관한 것으로, SOI(Silicon-On Insulator) 기판을 이용하여 2개의 실리콘 핀(fin)이 수직으로 적층된 구조를 형성하고, 상부 실리콘 핀의 4측면과 하부 실리콘 핀의 3측면을 채널로 이용함으로써 채널 폭이 증가되어 소자의 전류구동력이 향상되고, 공정의 최적화 및 안정화를 통해 저전력 및 고성능의 나노급 반도체 집적회로(IC) 및 고집적 메모리 집적회로(IC)를 제작할 수 있다.
Abstract:
본 발명은 초박형 SOI 웨이퍼 제조 방법에 관해 개시한다. 내부에는 수소 주입층 및 매몰 산화층이 형성되고, 표면에는 산화막이 형성된 콘트롤 웨이퍼를 준비한다. 상기 콘트롤 웨이퍼의 산화막 표면에 핸들 웨이퍼를 접합한 후 스마트 컷 방법으로 상기 수소 주입층 하부의 콘트롤 웨이퍼를 제거한다. 상기 매몰 산화층 상부의 실리콘 및 상기 매몰 산화층을 제거한 후 노출되는 실리콘을 소정 두께 연마한다. 본 발명의 SOI 웨이퍼는 웨이퍼 수준에서 높은 두께 균일도와 우수한 막질을 갖는 실리콘 활성층을 포함하며, 저비용으로 제조가 가능하다.
Abstract:
An extended drain metal oxide semiconductor field effect transistor (EDMOSFET) with a source field plate is provided. The EDMOSFET includes: a first-conductivity type semiconductor substrate; a first-conductivity type well region formed in the semiconductor substrate; a second-conductivity type drift region formed in a predetermined upper region of the well region; a heavily doped second-conductivity type drain region formed in a predetermined upper region of the drift region; a heavily doped second-conductivity type source region formed in the predetermined upper region of the well region with a predetermined gap separation from the drift region; a gate insulating layer formed on the surface of the well region between the drift region and the source region; a gate conductive layer formed on the gate insulating layer; a first interlayer dielectric layer covering portions of the surfaces of the source region and the drift regions and the gate conductive layer; a source field plate formed on the first interlayer dielectric layer; a second interlayer dielectric layer covering the source field plate and partially exposing the surfaces of the source region and the drain region; a source electrode formed in contact with the exposed surface of the source region and electrically connected to the source field plate; and a drain electrode formed in contact with the exposed surface of the drain region.
Abstract:
PURPOSE: A data bus system for a microcontroller is provided to increase an operation speed and reduce power consumption by reducing load capacitance of a data bus forming the data bus system. CONSTITUTION: An external access bus(204) is used by the data out from a CPU(214) and the data entering an I/O(Input/Output)(212) or an internal memory(216) from the outside. An internal access bus(202) is used by the data entering the CPU, the data out from the I/O or the internal memory, and the data out from or entering a peripheral circuit(218). An internal memory test bus(206) is used by the data out through the I/O. The external and the internal access bus are connected with each other through a latch structure(208).
Abstract:
The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.
Abstract:
The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the trench between the high-voltage high-power device and the logic CMOS device and can easily control the concentration of a deep well.
Abstract:
PURPOSE: A method for fabricating a Bipolar-CMOS-DMOS(BCD) device is provided to fabricate a BCD device that has voltage tolerance of 20-30 volt and 60-90 volt and gate oxide layers of different thicknesses by using a CMOS device process of a submicron class. CONSTITUTION: Only a drift region is formed under a drain region of a lateral double diffused MOS(LDMOS) device of 20-30 volt class while a drift region is formed under a drain region of 60-90 volt class so that a well region is formed to improve voltage tolerance and an on-resistance characteristic. A gate oxide layer of an nLDMOS device is made thin while a gate oxide layer of a pLDMOS device is made thick so that a gate apply voltage is increased to improve driving capability. A device occupying area is reduced by isolating devices while using a trench. A drift region of a DMOS device is formed to simplify a process by using a mask for forming the base of a bipolar device.
Abstract:
PURPOSE: An extended drain metal oxide semiconductor(EDMOS) device with the structure of lattice type drift region is provided to simultaneously obtain a high breakdown voltage and low on-resistance by making an np junction composed of a high density n lattice and a low density p lattice. CONSTITUTION: A well region(204) is formed in a predetermined region on a silicon substrate(201). A lattice-type drift region in which the first lattice and the second lattice are repeatedly arranged in every direction while contacting each other is formed in a predetermined region of the well region. A field oxide layer is formed in a predetermined portion of the well region or in predetermined portions of the well region and the drift region. A drain region(213) is formed in a predetermined region inside the drift region. A diffusion region is formed under the drain region. A source region(212) and a source contact region(214) are formed in a predetermined region of the well region. A gate electrode is formed in a predetermined region on the well region by interposing a gate insulation layer. A source electrode(216) is connected to the source region and the source contact region. A drain electrode(217) is connected to the drain region.