제조 공정과 특성 제어가 용이한 전력 집적회로 구조
    92.
    发明授权
    제조 공정과 특성 제어가 용이한 전력 집적회로 구조 失效
    一种用于简化制造工艺和特性控制的电源IC结构

    公开(公告)号:KR100534601B1

    公开(公告)日:2005-12-07

    申请号:KR1019990033494

    申请日:1999-08-14

    Abstract: 본 발명은 반도체 기술에 관한 것으로, 특히 제조 공정과 특성 제어가 용이한 전력 집적회로(Integrated Circuit, IC)에 관한 것이며, 그 불순물 확산 영역 형성이 용이하여, 소자의 특성을 용이하게 제어할 수 있는 구조를 가진 전력 집적회로를 제공하는데 그 목적이 있다. 본 발명은 SOI(Silicon-On-Insulator) 기판의 활성 실리콘층에 제공되는 제1 도전형-LDMOS(Lateral Double-diffused Metal Oxide Semiconductor) 트랜지스터, 제2 도전형-LDMOS 트랜지스터 및 CMOS(Complementary Metal Oxide Semiconductor) 트랜지스터를 구비한 전력 집적회로에 있어서, 상기 제1 도전형-LDMOS 트랜지스터가 상기 활성 실리콘층 내의 깊은 제2 도전형 웰에 RESURF(REduced-SURface Field)형으로 제공되며, 상기 제2 도전형-LDMOS 트랜지스터가 상기 활성 실리콘층 내의 깊은 제2 도전형 웰에 비-RESURF형으로 제공되는 것을 특징으로 한다.

    SOI 웨이퍼 제조 방법
    94.
    发明公开
    SOI 웨이퍼 제조 방법 失效
    绝缘子波导硅制造方法

    公开(公告)号:KR1020050060170A

    公开(公告)日:2005-06-22

    申请号:KR1020030091708

    申请日:2003-12-16

    Abstract: 본 발명은 초박형 SOI 웨이퍼 제조 방법에 관해 개시한다. 내부에는 수소 주입층 및 매몰 산화층이 형성되고, 표면에는 산화막이 형성된 콘트롤 웨이퍼를 준비한다. 상기 콘트롤 웨이퍼의 산화막 표면에 핸들 웨이퍼를 접합한 후 스마트 컷 방법으로 상기 수소 주입층 하부의 콘트롤 웨이퍼를 제거한다. 상기 매몰 산화층 상부의 실리콘 및 상기 매몰 산화층을 제거한 후 노출되는 실리콘을 소정 두께 연마한다. 본 발명의 SOI 웨이퍼는 웨이퍼 수준에서 높은 두께 균일도와 우수한 막질을 갖는 실리콘 활성층을 포함하며, 저비용으로 제조가 가능하다.

    소스 필드 플레이트를 갖는 드레인 확장형 모스 전계 효과트랜지스터 및그 제조방법
    95.
    发明授权
    소스 필드 플레이트를 갖는 드레인 확장형 모스 전계 효과트랜지스터 및그 제조방법 失效
    소스필드플레이트를갖는드레이확확장형모스전계효과트랜스터터및및그제조방

    公开(公告)号:KR100445904B1

    公开(公告)日:2004-08-25

    申请号:KR1020010078666

    申请日:2001-12-12

    Inventor: 이대우 김종대

    CPC classification number: H01L29/402 H01L29/66659 H01L29/7835

    Abstract: An extended drain metal oxide semiconductor field effect transistor (EDMOSFET) with a source field plate is provided. The EDMOSFET includes: a first-conductivity type semiconductor substrate; a first-conductivity type well region formed in the semiconductor substrate; a second-conductivity type drift region formed in a predetermined upper region of the well region; a heavily doped second-conductivity type drain region formed in a predetermined upper region of the drift region; a heavily doped second-conductivity type source region formed in the predetermined upper region of the well region with a predetermined gap separation from the drift region; a gate insulating layer formed on the surface of the well region between the drift region and the source region; a gate conductive layer formed on the gate insulating layer; a first interlayer dielectric layer covering portions of the surfaces of the source region and the drift regions and the gate conductive layer; a source field plate formed on the first interlayer dielectric layer; a second interlayer dielectric layer covering the source field plate and partially exposing the surfaces of the source region and the drain region; a source electrode formed in contact with the exposed surface of the source region and electrically connected to the source field plate; and a drain electrode formed in contact with the exposed surface of the drain region.

    Abstract translation: 提供具有源极场板的扩展漏极金属氧化物半导体场效应晶体管(EDMOSFET)。 该EDMOSFET包括:第一导电类型的半导体衬底; 形成在半导体衬底中的第一导电类型阱区; 形成在阱区的预定上部区域中的第二导电类型漂移区; 重掺杂的第二导电类型漏极区域,形成在漂移区域的预定上部区域中; 重掺杂的第二导电类型源极区域,所述重掺杂的第二导电类型源极区域与所述漂移区域以预定间隙分离形成在所述阱区域的预定上部区域中; 在漂移区和源极区之间的阱区的表面上形成的栅极绝缘层; 栅极导电层,形成在栅极绝缘层上; 第一层间电介质层,覆盖所述源极区和所述漂移区以及所述栅极导电层的表面的一部分; 形成在第一层间介电层上的源极场板; 第二层间介电层,覆盖所述源极场板并部分暴露所述源极区和所述漏极区的表面; 形成为与源极区的暴露表面接触并电连接到源极场板的源极; 以及形成为与漏极区的暴露表面接触的漏极。

    마이크로 컨트롤러를 위한 데이터 버스 시스템
    96.
    发明公开
    마이크로 컨트롤러를 위한 데이터 버스 시스템 有权
    MICROCONTROLLER数据总线系统

    公开(公告)号:KR1020040032376A

    公开(公告)日:2004-04-17

    申请号:KR1020020061487

    申请日:2002-10-09

    CPC classification number: G06F13/4217 Y02D10/14 Y02D10/151

    Abstract: PURPOSE: A data bus system for a microcontroller is provided to increase an operation speed and reduce power consumption by reducing load capacitance of a data bus forming the data bus system. CONSTITUTION: An external access bus(204) is used by the data out from a CPU(214) and the data entering an I/O(Input/Output)(212) or an internal memory(216) from the outside. An internal access bus(202) is used by the data entering the CPU, the data out from the I/O or the internal memory, and the data out from or entering a peripheral circuit(218). An internal memory test bus(206) is used by the data out through the I/O. The external and the internal access bus are connected with each other through a latch structure(208).

    Abstract translation: 目的:提供微控制器的数据总线系统,通过减少形成数据总线系统的数据总线的负载电容来提高运行速度并降低功耗。 构成:外部访问总线(204)由CPU(214)输出的数据和从外部进入I / O(输入/输出)(212)或内部存储器(216)的数据)使用。 内部访问总线(202)由进入CPU的数据,来自I / O或内部存储器的数据以及从外围电路(218)输出或进入外围电路(218)的数据使用。 内部存储器测试总线(206)由数据通过I / O使用。 外部和内部访问总线通过锁存结构(208)彼此连接。

    격자형 표류 영역 구조를 갖는 이디모스 소자 및 그 제조방법
    97.
    发明授权
    격자형 표류 영역 구조를 갖는 이디모스 소자 및 그 제조방법 失效
    이자형표류영역구조를갖는이디모스소자및그제조방

    公开(公告)号:KR100422393B1

    公开(公告)日:2004-03-11

    申请号:KR1020020002695

    申请日:2002-01-17

    CPC classification number: H01L29/0634 H01L29/7835

    Abstract: The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.

    Abstract translation: 本发明提供具有晶格型漂移区的EDMOS(扩展漏极MOS)器件及其制造方法。 在n沟道EDMOS(nEDMOS)的情况下,漂移区具有其中具有高浓度的n晶格和具有低浓度的p晶格交替排列的晶格结构。 当施加漏极电压时,耗尽层由n晶格和p晶格的pn结突然延伸,使得整个漂移区容易耗尽。 因此,器件的击穿电压增加,并且由于高浓度的n晶格,器件的导通电阻降低。

    전력 집적회로 소자의 제조 방법
    98.
    发明授权
    전력 집적회로 소자의 제조 방법 失效
    전력집적회로소자의제조방법

    公开(公告)号:KR100418435B1

    公开(公告)日:2004-02-14

    申请号:KR1020010085165

    申请日:2001-12-26

    CPC classification number: H01L27/1203 H01L21/84

    Abstract: The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the trench between the high-voltage high-power device and the logic CMOS device and can easily control the concentration of a deep well.

    Abstract translation: 本发明涉及一种使用SOI结构的衬底制造高压大功率集成电路器件的方法,其中绝缘膜和硅层依次堆叠在硅衬底上。 该方法包括以下步骤:在硅层上顺序形成氧化膜和光致抗蚀剂膜,然后使用沟槽掩模执行光刻工艺以图案化光致抗蚀剂膜; 使用图案化的光致抗蚀剂膜作为掩模来图案化氧化物膜,然后去除图案化之后残留的光致抗蚀剂膜; 使用图案化的氧化物膜作为掩模来蚀刻硅层,直到绝缘膜被暴露以形成沟槽; 在包括沟槽的整个表面上形成氮化物膜,执行退火工艺并且在整个表面上沉积多晶硅以便埋入沟槽; 并依次去除多晶硅和氮化物膜直到硅层暴露以使表面变平,从而形成用于沟槽内器件之间的电隔离的器件隔离膜。 因此,本发明可以有效地减少高压大功率器件与逻辑CMOS器件之间的沟槽的隔离区域,并且可以容易地控制深阱的浓度。

    비씨디 소자 및 그 제조 방법
    99.
    发明授权
    비씨디 소자 및 그 제조 방법 失效
    비씨디소자및그제조방법

    公开(公告)号:KR100403053B1

    公开(公告)日:2003-10-23

    申请号:KR1020010073392

    申请日:2001-11-23

    Abstract: PURPOSE: A method for fabricating a Bipolar-CMOS-DMOS(BCD) device is provided to fabricate a BCD device that has voltage tolerance of 20-30 volt and 60-90 volt and gate oxide layers of different thicknesses by using a CMOS device process of a submicron class. CONSTITUTION: Only a drift region is formed under a drain region of a lateral double diffused MOS(LDMOS) device of 20-30 volt class while a drift region is formed under a drain region of 60-90 volt class so that a well region is formed to improve voltage tolerance and an on-resistance characteristic. A gate oxide layer of an nLDMOS device is made thin while a gate oxide layer of a pLDMOS device is made thick so that a gate apply voltage is increased to improve driving capability. A device occupying area is reduced by isolating devices while using a trench. A drift region of a DMOS device is formed to simplify a process by using a mask for forming the base of a bipolar device.

    Abstract translation: 目的:提供一种用于制造双极-CMOS-DMOS(BCD)器件的方法,以通过使用CMOS器件工艺制造具有20-30伏和60-90伏的电压容差的BCD器件和不同厚度的栅氧化层 亚微米级的。 构成:在20-30伏特级别的横向双扩散MOS(LDMOS)器件的漏极区域下方仅形成漂移区域,而在60-90伏特的漏极区域下方形成漂移区域,使得阱区域 形成以改善电压容限和导通电阻特性。 使nLDMOS器件的栅极氧化层变薄,同时使pLDMOS器件的栅极氧化层变厚,从而提高栅极施加电压以提高驱动能力。 在使用沟槽时,通过隔离设备来减少设备占用面积。 通过使用用于形成双极器件的基极的掩模来形成DMOS器件的漂移区以简化工艺。

    격자형 표류 영역 구조를 갖는 이디모스 소자 및 그 제조방법
    100.
    发明公开
    격자형 표류 영역 구조를 갖는 이디모스 소자 및 그 제조방법 失效
    延伸型金属氧化物半导体器件,具有延伸型移动区域的结构及其制造方法

    公开(公告)号:KR1020030062489A

    公开(公告)日:2003-07-28

    申请号:KR1020020002695

    申请日:2002-01-17

    CPC classification number: H01L29/0634 H01L29/7835

    Abstract: PURPOSE: An extended drain metal oxide semiconductor(EDMOS) device with the structure of lattice type drift region is provided to simultaneously obtain a high breakdown voltage and low on-resistance by making an np junction composed of a high density n lattice and a low density p lattice. CONSTITUTION: A well region(204) is formed in a predetermined region on a silicon substrate(201). A lattice-type drift region in which the first lattice and the second lattice are repeatedly arranged in every direction while contacting each other is formed in a predetermined region of the well region. A field oxide layer is formed in a predetermined portion of the well region or in predetermined portions of the well region and the drift region. A drain region(213) is formed in a predetermined region inside the drift region. A diffusion region is formed under the drain region. A source region(212) and a source contact region(214) are formed in a predetermined region of the well region. A gate electrode is formed in a predetermined region on the well region by interposing a gate insulation layer. A source electrode(216) is connected to the source region and the source contact region. A drain electrode(217) is connected to the drain region.

    Abstract translation: 目的:提供具有晶格型漂移区结构的延伸漏极金属氧化物半导体(EDMOS)器件,通过使np结构成高密度n格和低密度,同时获得高击穿电压和低导通电阻 p格。 构成:在硅衬底(201)上的预定区域中形成阱区(204)。 在阱区域的预定区域中形成格子型漂移区域,其中第一晶格和第二晶格在彼此接触的情况下沿每个方向重复布置。 在阱区域的预定部分或阱区域和漂移区域的预定部分中形成场氧化物层。 漏极区域(213)形成在漂移区域内的预定区域中。 在漏极区域下方形成扩散区域。 源区域(212)和源极接触区域(214)形成在阱区域的预定区域中。 通过设置栅极绝缘层,在阱区的预定区域中形成栅电极。 源极(216)连接到源区和源极接触区。 漏电极(217)连接到漏区。

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