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公开(公告)号：CA3132753A1
公开(公告)日：2020-09-17
申请号：CA3132753
申请日：2020-02-26
Applicant: IBM
Inventor： HELLER LISA , BUSABA FADI , BRADBURY JONATHAN , BORNTRAEGER CHRISTIAN , BACHER UTZ , BUENDGEN REINHARD
Abstract: A method is provided. The method is implemented by a communication interface of a secure interface control executing between the secure interface control of a computer and hardware of the computer/ In this regard, the communication interface receives an instruction and determines whether the instruction is a millicoded instruction. Further, the communication interface enters a millimode comprising enabling the secure interface control to engage millicode of the hardware through the communication interface based on the instruction being the millicoded instruction. The millicode, then, executes the instruction
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92.发明专利
公开(公告)号：CA3132752A1
公开(公告)日：2020-09-17
申请号：CA3132752
申请日：2020-02-28
Applicant: IBM
Inventor： BORNTRAEGER CHRISTIAN , IMBRENDA CLAUDIO , BUSABA FADI , BRADBURY JONATHAN , HELLER LISA
Abstract: A method is provided by a secure interface control of a computer that provides a partial instruction interpretation for an instruction which enables an interruption. The secure interface control fetches a program status word or a control register value from a secure guest storage. The secure interface control notifies an untrusted entity of guest interruption mask updates. The untrusted entity is executed on and in communication with hardware of the computer through the secure interface control to support operations of a secure entity executing on the untrusted entity. The secure interface control receives, from the untrusted entity, a request to present a highest priority, enabled guest interruption in response to the notifying of the guest interruption mask updates. The secure interface control moves interruption information into a guest prefix page and injecting the interruption in the secure entity when an injection of the interruption is determined to be valid.
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公开(公告)号：CA3132735A1
公开(公告)日：2020-09-17
申请号：CA3132735
申请日：2020-02-17
Applicant: IBM
Inventor： BUENDGEN REINHARD , BORNTRAEGER CHRISTIAN , BRADBURY JONATHAN , BUSABA FADI , HELLER LISA , MIHAJLOVSKI VIKTOR
Abstract: Secure processing within a computing environment is provided by incrementally decrypting a secure operating system image, including receiving, for a page of the secure operating system image, a page address and a tweak value used during encryption of the page. Processing determines that the tweak value has not previously been used during decryption of another page of the secure operating system image, and decrypts memory page content at the page address using an image encryption key and the tweak value to facilitate obtaining a decrypted secure operating system image. Further, integrity of the secure operating system image is verified, and based on verifying integrity of the secure operating system image, execution of the decrypted secure operating system image is started.
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94.发明专利
公开(公告)号：HUE046174T2
公开(公告)日：2020-02-28
申请号：HUE15763327
申请日：2015-09-14
Applicant: IBM
Inventor： HELLER LISA , BUSABA FADI , BRADBURY JONATHAN , FARRELL MARK , GREINER DAN , KUBALA JEFFREY , OSISEK DAMIAN , SLEGEL TIMOTHY , SCHMIDT DONALD
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公开(公告)号：CA2701086C
公开(公告)日：2017-09-19
申请号：CA2701086
申请日：2009-01-05
Applicant: IBM
Inventor： GREINER DAN , GAINEY JR CHARLES , HELLER LISA , OSISEK DAMIAN , SLEGEL TIMOTHY , SITTMANN III GUSTAV
IPC: G06F9/30 , G06F12/1009 , G06F12/14
Abstract: What is disclosed is a set key and clear frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which identifies a first and second general register. Obtained from the first general register is a frame size field indicating whether a storage frame is one of a small block or a large block of data. Obtained from the second general register is an operand address of a storage frame upon which the instruction is to be performed. If the storage frame is a small block, the instruction is performed only on the small block. If the indicated storage frame is a large block of data, an operand address of an initial first block of data within the large block of data is obtained from the second general register. The frame management instruction is performed on all blocks starting from the initial first block.
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Patent Agency Ranking
公开(公告)号：AU2015330266A1
公开(公告)日：2017-03-09
申请号：AU2015330266
申请日：2015-09-14
Applicant: IBM
Inventor： FARRELL MARK , HELLER LISA , KUBALA JEFFREY PAUL , SCHMIDT DONALD WILLIAM , GREINER DAN , SLEGEL TIMOTHY , BUSABA FADI YUSUF , OSISEK DAMIAN , BRADBURY JONATHAN DAVID , LEHNERT FRANK , NERZ BERND , JACOBI CHRISTIAN
Abstract: A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.
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公开(公告)号：BRPI0906426A2
公开(公告)日：2016-10-11
申请号：BRPI0906426
申请日：2009-01-05
Applicant: IBM
Inventor： GAINEY CHARLES JR , OSISEK DAMIAN , GREINER DAN , SITTMANN GUSTAV III , HELLER LISA , SLEGEL TIMOTHY
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公开(公告)号：CY1113979T1
公开(公告)日：2016-07-27
申请号：CY131100366
申请日：2013-05-02
Applicant: IBM
Inventor： GREINER DAN , HELLER LISA , OSISEK DAMIAN , SLEGEL TIMOTHY , PFEFFER ERWIN , WEBB CHARLES
IPC: G06F12/10
Abstract: Αυτόπουπαρέχεταιείναιμίαευκολίαβελτιωμένηςδυναμικήςμεταφράσεωςδιευθύνσεως. Σεμίαυλοποίηση, λαμβάνονται, μίαεικονικήδιεύθυνσηπροςμετάφρασηκαιμίααρχικήδιεύθυνσηπροελεύσεωςενόςπίνακαμεταφράσεωςμίαςιεραρχίαςπινάκωνμεταφράσεως. Χρησιμοποιείταιένατμήμαδείκτητηςεικονικήςδιευθύνσεωςγιαναγίνειαναφοράσεμίαεισαγωγήστονπίνακαμεταφράσεως. Εάνέχειενεργοποιηθείτοπεδίοελέγχουμορφοτύπου, λαμβάνεταιμίαδιεύθυνσηπλαισίουενόςμεγάλουμπλοκδεδομένωνστηνκύριαμνήμηαπότηνεισαγωγήπίνακαμεταφράσεως. Τομεγάλομπλοκδεδομένωνείναιέναμπλοκμεγέθουςτουλάχιστον 1Mbyte. Ηδιεύθυνσηπλαισίουσυνδυάζεταικατόπινμεένατμήμαμετατοπίσεωςτηςεικονικήςδιευθύνσεωςγιανασχηματισθείη μεταφρασθείσαδιεύθυνσηενόςεπιθυμητούμπλοκδεδομένωνεντόςτουμεγάλουμπλοκδεδομένωνστηνκύριαμνήμη. Γίνεταικατόπινπροσπέλασητουεπιθυμητούμεγάλουμπλοκδεδομένωνπουδιευθυνσιοδοτείταιαπότημεταφρασθείσαδιεύθυνση.
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公开(公告)号：AU2010355814B2
公开(公告)日：2014-05-15
申请号：AU2010355814
申请日：2010-11-08
Applicant: IBM
Inventor： GREINER DAN , OSISEK DAMIAN LEO , SLEGEL TIMOTHY , HELLER LISA
Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.
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100.发明专利
公开(公告)号：PL2430532T3
公开(公告)日：2014-04-30
申请号：PL10775820
申请日：2010-11-08
Applicant: IBM
Inventor： GREINER DAN , OSISEK DAMIAN LEO , SLEGEL TIMOTHY , HELLER LISA
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