94.
    发明专利
    未知

    公开(公告)号:DE10204652A1

    公开(公告)日:2003-08-21

    申请号:DE10204652

    申请日:2002-02-05

    Abstract: Circuit arrangement having a sensor electrode, a first circuit unit, which is electrically coupled to the sensor electrode, and a second circuit unit, which has a first capacitor. The first circuit unit holds an electrical potential of the sensor electrode in a predetermined first reference range around a predetermined electrical desired potential by coupling the first capacitor and the sensor electrode such that there is a matching of their electrical potentials. If the second circuit unit detects the electrical potential of the first capacitor being outside a second reference range, the second circuit unit brings the first capacitor to a first electrical reference potential.

    95.
    发明专利
    未知

    公开(公告)号:DE50002394D1

    公开(公告)日:2003-07-03

    申请号:DE50002394

    申请日:2000-09-21

    Abstract: A multivalue magnetoresistive read/write memory and method of writing to and reading from such a memory. The invention has, inter alia, one or more storage cells, each storage cell having two intersecting electric conductors and a layer system comprising magnetic layers located at the intersection of the electric conductors. The memory is characterized in that the layer system is designated as a multilayer system with two or more magnetic layers, wherein at least two of the magnetic layers have a magnetization direction that can be set independently of one another. Further, the magnetization direction of the individual layers may be changed on the basis of the electric current flowing through the electric conductors.

    96.
    发明专利
    未知

    公开(公告)号:DE50000926D1

    公开(公告)日:2003-01-23

    申请号:DE50000926

    申请日:2000-03-13

    Abstract: A magnetoresistive memory is described and contains a common word line voltage source, bit lines, word lines crossing the bit lines, and a memory cell array having memory cells with cell resistors. The memory cell array further has reference cells with reference cell resistors. The memory cell array is configured such that for testing a respective cell resistor in each case two of the reference cell resistors nearest the respective cell resistor and the reference cell are simultaneously connected to a common word line voltage. A first feedback amplifier together with the two reference cell resistors form a summing amplifier. A second feedback amplifier together with the respective cell resistor form an amplifier having an equivalent gain as the summing amplifier. A comparator is connected to the summing amplifier and the amplifier. The comparator has an output supplying an evaluation signal dependent on the respective cell resistor.

    97.
    发明专利
    未知

    公开(公告)号:DE10112778A1

    公开(公告)日:2002-10-02

    申请号:DE10112778

    申请日:2001-03-16

    Abstract: The invention relates to a biosensor for detecting nucleic acids, comprising at least two units for immobilizing nucleic acids and one electrical detection circuit. Said units are electroconductive and electrically insulated from one another. The units are provided with first nucleic acid molecules that are present as single-stranded molecules and that are capable of binding second nucleic acids to be detected. These scavenger molecules are provided with a redox-active marker that is capable of producing a detectable signal. The electrical detection circuit is adapted to detect by means of the marker any nucleic acid molecules bound to the scavenger molecules.

    98.
    发明专利
    未知

    公开(公告)号:DE10060432A1

    公开(公告)日:2002-07-25

    申请号:DE10060432

    申请日:2000-12-05

    Abstract: A magnetoresistive memory includes a control circuit with a first pole that, via a reading distributor, can be individually connected to first ends of bit lines by switching elements. The control circuit also has a second pole, which supplies power to an evaluator, and has a third pole that is connected to a reference voltage source. The readout circuit additionally includes a third voltage source having a voltage, which is approximately equal to the voltage of the first reading voltage source and which can be individually connected to second ends of the bit lines by means of switching elements. Finally, the readout circuit includes a fourth voltage source, which can be individually connected to second ends of the word lines by means of switching elements.

    Matrix capacitance evaluation circuit

    公开(公告)号:DE10010888A1

    公开(公告)日:2001-09-27

    申请号:DE10010888

    申请日:2000-03-06

    Abstract: The capacitance evaluation circuit has a test path (2) coupled to one electrode of each capacitance (Cchar) to be measured, for providing 2 different potentials (V1,V2) and a measuring path (3) coupled to the other electrode of the capacitance, having 2 parallel arms coupled to a common potential (V0), one of which contains a measuring instrument for evaluation of the capacitance. A control device allows each individual capacitance to be measured to be coupled to the 2 different potentials, using integrated switching transistors (T5,T6,T7,T8), using signals provided by an address decoder (10,11).

    100.
    发明专利
    未知

    公开(公告)号:AT205014T

    公开(公告)日:2001-09-15

    申请号:AT97930296

    申请日:1997-05-21

    Abstract: PCT No. PCT/DE97/01027 Sec. 371 Date Nov. 12, 1998 Sec. 102(e) Date Nov. 12, 1998 PCT Filed May 21, 1997 PCT Pub. No. WO97/47010 PCT Pub. Date Dec. 11, 1997In the read amplifier a mismatch of the inception voltages of cross-coupled transistors (M5, M6) of the read amplifier are compensated by four further transistors (M1 . . . M4), whereby a defined equalizing of the bitlines advantageously takes place with these further transistors simultaneously in what is called the equalize phase. The compensation takes place in that the bitline that is connected with the transistor with the lower inception voltage is charged to a higher level in the pre-load phase. This higher bitline level is switched to the gate of the transistor connected with the other bitline. In the evaluation phase the transistor with the higher inception voltage becomes more strongly conductive. Read amplifiers of this sort are most significant for memory generations beginning at 1 Gbit, since the mismatch due to the variation of the input voltages of the transistors can no longer usefully be solved by a correspondingly large gate surface of the cross-coupled transistors in the read amplifier.

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