公开(公告)号：DE10196006B4

公开(公告)日：2008-07-24

申请号：DE10196006

申请日：2001-03-14

Applicant: INTEL CORP

Inventor： ELLISON CARL M ,  GOLLIVER ROGER A ,  HERBERT HOWARD C ,  LIN DERRICK C ,  MCKEEN FRANCIS X ,  NEIGER GILBERT ,  RENERIS KEN ,  SUTTON JAMES A ,  THAKKAR SHREEKANT S ,  MITTAL MILLIND

IPC: G06F1/00 ,  G06F21/22 ,  G06F21/00 ,  G09C1/00 ,  H04L9/08 ,  H04L9/10

Abstract: The present invention is a method, apparatus, and system to generate a key hierarchy for use in an isolated execution environment of a protected platform. In order to bind secrets to particular code operating in isolated execution, a key hierarchy comprising a series of symmetric keys for a standard symmetric cipher is utilized. The protected platform includes a processor that is configured in one of a normal execution mode and an isolated execution mode. A key storage stores an initial key that is unique for the platform. A cipher key creator located in the protected platform creates the hierarchy of keys based upon the initial key. The cipher key creator creates a series of symmetric cipher keys to protect the secrets of loaded software code.

公开(公告)号：DE69736956T2

公开(公告)日：2007-09-20

申请号：DE69736956

申请日：1997-09-29

Applicant: INTEL CORP

Inventor： MITTAL MILLIND ,  VALENTINE ROBERT

IPC: G06F1/32

公开(公告)号：DE69730164T2

公开(公告)日：2005-08-04

申请号：DE69730164

申请日：1997-12-12

Applicant: INTEL CORP

Inventor： MITTAL MILLIND

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F13/16

公开(公告)号：GB2405974B

公开(公告)日：2005-04-27

申请号：GB0426493

申请日：2001-03-21

Applicant: INTEL CORP

Inventor： HERBERT HOWARD C ,  GRAWROCK DAVID W ,  ELLISON CARL M ,  GOLLIVER ROGER A ,  LIN DERRICK C ,  MCKEEN FRANCIS X ,  RENERIS KEN ,  SUTTON JAMES A ,  THAKKAR SHREEKANT S ,  MITTAL MILLIND ,  NEIGER GILBERT

IPC: G06F1/00 ,  G06F21/57

公开(公告)号：GB2405973B

公开(公告)日：2005-04-27

申请号：GB0426491

申请日：2001-03-21

Applicant: INTEL CORP

Inventor： HERBERT HOWARD ,  GRAWROCK DAVID W ,  ELLISON CARL M ,  GOLLIVER ROGER A ,  LIN DERRICK C ,  MCKEEN FRANCIS X ,  RENERIS KEN ,  SUTTON JAMES A ,  THAKKAR SHREEKANT S ,  MITTAL MILLIND ,  NEIGER GILBERT

IPC: G06F1/00 ,  G06F21/57

公开(公告)号：GB2405973A

公开(公告)日：2005-03-16

申请号：GB0426491

申请日：2001-03-21

Applicant: INTEL CORP

Inventor： HERBERT HOWARD ,  GRAWROCK DAVID W ,  ELLISON CARL M ,  GOLLIVER ROGER A ,  LIN DERRICK C ,  MCKEEN FRANCIS X ,  RENERIS KEN ,  SUTTON JAMES A ,  THAKKAR SHREEKANT S ,  MITTAL MILLIND ,  NEIGER GILBERT

IPC: G06F1/00 ,  G06F21/57

Abstract: A method of remote attestation for a special mode of operation comprises storing an audit log within protected memory of a platform. The audit log is a listing of data representing each of a plurality of Iso X software modules loaded into the platform. The audit log is retrieved from the protected memory in response to receiving a remote attestation request from a remotely located platform. Then, the retrieved audit log is digitally signed to produce a digital signature for transfer to the remotely located platform.

公开(公告)号：GB2377794B

公开(公告)日：2005-02-16

申请号：GB0225050

申请日：2001-03-21

Applicant: INTEL CORP

Inventor： HERBERT HOWARD C ,  GRAWROCK DAVID W ,  ELLISON CARL M ,  GOLLIVER ROGER A ,  LIN DERRICK C ,  MCKEEN FRANCIS X ,  PORSCHE AKTIENGESELLSCHAFT DR ,  RENERIS KEN ,  SUTTON JAMES A ,  THAKKAR SHREEKANT S ,  MITTAL MILLIND ,  NEIGER GILBERT

IPC: G06F1/00 ,  G06F12/14 ,  G06F21/00

公开(公告)号：HK1057108A1

公开(公告)日：2004-03-12

申请号：HK03107535

申请日：1998-03-16

Applicant: INTEL CORP

Inventor： PELEG ALEXANDER ,  YAARI YAAKOV ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY

IPC: G06F20060101 ,  G06F5/00 ,  G06F9/305 ,  G06F7/52 ,  G06F9/30 ,  G06F9/302 ,  G06F9/38

Abstract: A processor (109) includes a decoder (202) being coupled to receive a control signal (207). The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data multiply operation is to be performed. The processor further includes a circuit (203) being coupled to the decoder. The circuit is for multiplying a first packed data being stored at the first location with a second packed data being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.

公开(公告)号：DE10196005T1

公开(公告)日：2003-03-13

申请号：DE10196005

申请日：2001-03-23

Applicant: INTEL CORP

Inventor： ELLISON CARL M ,  GOLLIVER ROGER A ,  HERBERT HOWARD C ,  LIN DERRICK C ,  MCKEEN FRANCIS X ,  NEIGER GILBERT ,  RENERIS KEN ,  SUTTON JAMES A ,  THAKKAR SHREEKANT S ,  MITTAL MILLIND

IPC: G06F9/46 ,  G06F1/00 ,  G06F9/48 ,  G06F21/00

Abstract: A technique is provided to execute isolated instructions according to an embodiment of the present invention. An execution unit executes an isolated instruction in a processor operating in a platform. The processor is configured in one of a normal execution mode and an isolated execution mode. A parameter storage containing at least one parameter to support execution of the isolated instruction when the processor is configured in the isolated execution mode.

公开(公告)号：AU4921801A

公开(公告)日：2001-10-15

申请号：AU4921801

申请日：2001-03-14

Applicant: INTEL CORP

Inventor： ELLISON CARL M ,  GOLLIVER ROGER A ,  HERBERT HOWARD C ,  LIN DERRICK C ,  MCKEEN FRANCIS X ,  NEIGER GILBERT ,  RENERIS KEN ,  SUTTON JAMES A ,  THAKKAR SHREEKANT S ,  MITTAL MILLIND

IPC: G06F21/00 ,  G06F9/00

Abstract: An access transaction generated by a processor is configured using a configuration storage containing a configuration setting. The processor has a normal execution mode and an isolated execution mode. The access transaction has access information. Access to the configuration storage is controlled. An access grant signal is generated using the configuration setting and the access information. The access grant signal indicates if the access transaction is valid.