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公开(公告)号：JP2006172486A
公开(公告)日：2006-06-29
申请号：JP2005364534
申请日：2005-12-19
Applicant: Intel Corp , インテル・コーポレーション
Inventor： PELEG ALEXANDER , YAAKOV YAARI , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY
CPC classification number: G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30167
Abstract: PROBLEM TO BE SOLVED: To perform a shift operation on a packed data type. SOLUTION: An apparatus for arithmetic operation is provided with: a shifter which performs a shift operation on a first packed data having a plurality of first data elements by a shift count in order to produce a second packed data having a plurality of second data elements; and a correction circuit which replaces at least one number of each of the plurality of second data elements and replaces all the replaced numbers corresponding to the shifted data element with number having the same value even in any data element of the shifted data elements. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：对打包数据类型执行移位操作。 解决方案：一种用于算术运算的装置具有：移位器，其通过移位计数对具有多个第一数据元素的第一打包数据执行移位操作，以便产生具有多个第二数据元素的第二打包数据 数据元素; 以及校正电路，其替换多个第二数据元素中的每一个的至少一个，并且即使在移位的数据元素的任何数据元素中，也替换与具有相同值的数字的移位数据元素相对应的所有替换数字。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：ZA9510127B
公开(公告)日：1996-06-06
申请号：ZA9510127
申请日：1995-11-29
Applicant: INTEL CORP
Inventor： PELEG ALEXANDER , YAARI YAAKOV , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY
Abstract: A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.
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公开(公告)号：EP0795155A4
公开(公告)日：1999-08-11
申请号：EP95944602
申请日：1995-12-01
Applicant: INTEL CORP
Inventor： PELEG ALEXANDER , YAARI YAAKOV , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY
CPC classification number: G06F7/53 , G06F7/49921 , G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/3885 , G06F2207/3828
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公开(公告)号：EP0795153A4
公开(公告)日：2001-11-14
申请号：EP95943362
申请日：1995-12-01
Applicant: INTEL CORP
Inventor： PELEG ALEXANDER , YAARI YAAKOV , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY
CPC classification number: G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
Abstract: A processor includes a first register (209) for storing a first packed data, a decoder (202), and a functional unit (203). The decoder has a control signal input (207) for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation, and the second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder (202) and the register (209). The functional unit performs the pack operation and the unpack operation using the first packed data as well as move operation.
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公开(公告)号：EP0795154A4
公开(公告)日：1999-03-10
申请号：EP95943654
申请日：1995-12-01
Applicant: INTEL CORP
Inventor： PELEG ALEXANDER , YAARI YAAKOV , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY
CPC classification number: G06F9/30014 , G06F7/026 , G06F9/30021 , G06F9/30036 , G06F2207/3828
Abstract: A processor includes a decoder (202) coupled to receive a control signal (207). The control signal has a first source address (602), a second source address (603), a destination address (605), and an operation field (601). The first source address corresponds to a first location, and the second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data compare operation is to be performed. The processor includes a circuit coupled to the decoder for comparing a first packed data being stored at the first location with a second packed data being stored at the second location and for communicating a corresponding result packed data to the third location.
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Patent Agency Ranking
公开(公告)号：GB2326494B
公开(公告)日：2000-08-23
申请号：GB9811430
申请日：1996-12-17
Applicant: INTEL CORP
Inventor： GLEW ANDREW F , VAKKALAGADDA RAMAMOHAN R , LIN DERRICK , MENNEMEIER LARRY M , PELEG ALEXANDER , BISTRY DAVID , MITTAL MILIND , DULONG CAROLE , KOWASHI EIICHI , EITAN BENNY
Abstract: A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file. Furthermore, the data processing apparatus alters all tags in a set of tags corresponding to the single logical register file to a non-empty state sometime between starting the execution of the first set of instructions and completing the execution of the first instruction. The tags identifying whether registers in the single logical register file are empty or non-empty.
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公开(公告)号：AU4738396A
公开(公告)日：1996-06-19
申请号：AU4738396
申请日：1995-12-01
Applicant: INTEL CORP
Inventor： PELEG ALEXANDER , YAARI YAAKOV , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY
Abstract: A processor (109) includes a decoder (202) being coupled to receive a control signal (207). The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data multiply operation is to be performed. The processor further includes a circuit (203) being coupled to the decoder. The circuit is for multiplying a first packed data being stored at the first location with a second packed data being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.
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公开(公告)号：AU4464596A
公开(公告)日：1996-06-19
申请号：AU4464596
申请日：1995-12-01
Applicant: INTEL CORP
Inventor： PELEG ALEXANDER , YAARI YAAKOV , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY
Abstract: A processor includes a first register (209) for storing a first packed data, a decoder (202), and a functional unit (203). The decoder has a control signal input (207) for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation, and the second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder (202) and the register (209). The functional unit performs the pack operation and the unpack operation using the first packed data as well as move operation.
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公开(公告)号：CA2205830C
公开(公告)日：2000-08-15
申请号：CA2205830
申请日：1995-12-01
Applicant: INTEL CORP
Inventor： YAARI YAAKOV , MITTAL MILLIND , PELEG ALEXANDER , EITAN BENNY , MENNENEIER LARRY M
Abstract: The processor (109) includes a decoder (202) being coupled to receive a control signal (207). The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit (203) being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.
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公开(公告)号：GB2321733B
公开(公告)日：2000-04-26
申请号：GB9811432
申请日：1996-12-10
Applicant: INTEL CORP
Inventor： DULONG CAROLE , PELEG ALEXANDER , MENNEMEIER LARRY M
Abstract: A computer system which manipulates audio and video signals. A multimedia input device which generates an audio and/or video signal is coupled to a processor. The processor is also coupled to a storage device upon which a decompression routine is stored, the decompression routine including a transposition routine. The transposition routine manipulates data elements associated with the audio or video signal in transposing an array of n rows of a plurality of data elements. The transposition routine causes the processor to interleave data elements from a first row with data elements from a second row to generate a first result. Data elements from a third row are interleaved with data elements from a fourth row to generate a second result. Then, data elements from the first result are interleaved with data elements from the second result to generate a third result.\!
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