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113 records (took 0.023 seconds)

    91.
    发明专利
    未知

    公开(公告)号：NO20032352L

    公开(公告)日：2003-07-23

    申请号：NO20032352

    申请日：2003-05-26

    Applicant: QUALCOMM INC

    Inventor： EASTON KENNETH D ,  BLACK PETER J

    IPC: H04B1/707 ,  H04B1/709 ,  H04B1/7093 ,  H04Q7/38

    Abstract: A receiver unit includes a first buffer that receives and stores digitized samples at a particular sample rate and a data processor that retrieves segments of digitized samples from the first buffer and processes the retrieved segments with a particular set of parameters values. The data processor is operated based on a processing clock having a frequency that is (e.g., then or more times) higher than the sample rate. Multiple instances of the received signal can be processed by retrieving and processing multiple segments of digitized samples from the first buffer, the receiver unit typically further includes a receiver that receives and processes a transmitted signal to provide the digitized samples and a controller that dispatches tasks for the data processor. The data processor can be designed to include a correlator, a symbol demodulation and combiner, a first accumulator, and a second buffer, or a combination thereof. The correlator despreads the retrieved segments of digitized samples with corresponding segments of PN despreading sequences to provide correlated samples, which are further processed by the symbol demodulation and combiner to provide processed symbols. The second buffer stores the processed symbols, and can be designed to provide de-interleaving of the processed symbols.

    92.
    发明专利
    未知

    公开(公告)号：AT243395T

    公开(公告)日：2003-07-15

    申请号：AT95937306

    申请日：1995-09-27

    Applicant: QUALCOMM INC

    Inventor： EASTON KENNETH D ,  LEVIN JEFFREY A

    IPC: H04L1/02 ,  H04B1/707 ,  H04B7/26 ,  H04J11/00 ,  H04J13/00 ,  H04L27/30 ,  H04Q7/20

    Abstract: An integrated search processor used in a modem for a spread spectrum communications system buffers receive samples and utilizes a time sliced transform processor operating on successive offsets from the buffer. The search processor autonomously steps through a search as configured by a microprocessor specified search parameter set, which can include the group of antennas to search over, the starting offset and width of the search window to search over, and the number of Walsh symbols to accumulate results at each offset. The search processor calculates the correlation energy at each offset, and presents a summary report of the best paths found in the search to use for demodulation element reassignment. This reduces the searching process related workload of the microprocessor and also reduces the modem costs by allowing a complete channel element modem circuit to be produced in a single IC.

    93.
    发明专利
    未知

    公开(公告)号：NO20032352D0

    公开(公告)日：2003-05-26

    申请号：NO20032352

    申请日：2003-05-26

    Applicant: QUALCOMM INC

    Inventor： EASTON KENNETH D ,  BLACK PETER J

    IPC: H04B1/707 ,  H04B1/709 ,  H04B1/7093 ,  H04Q7/38 ,  H04B

    Abstract: A receiver unit includes a first buffer that receives and stores digitized samples at a particular sample rate and a data processor that retrieves segments of digitized samples from the first buffer and processes the retrieved segments with a particular set of parameters values. The data processor is operated based on a processing clock having a frequency that is (e.g., then or more times) higher than the sample rate. Multiple instances of the received signal can be processed by retrieving and processing multiple segments of digitized samples from the first buffer, the receiver unit typically further includes a receiver that receives and processes a transmitted signal to provide the digitized samples and a controller that dispatches tasks for the data processor. The data processor can be designed to include a correlator, a symbol demodulation and combiner, a first accumulator, and a second buffer, or a combination thereof. The correlator despreads the retrieved segments of digitized samples with corresponding segments of PN despreading sequences to provide correlated samples, which are further processed by the symbol demodulation and combiner to provide processed symbols. The second buffer stores the processed symbols, and can be designed to provide de-interleaving of the processed symbols.

    94.
    发明专利
    未知

    公开(公告)号：ES2184871T3

    公开(公告)日：2003-04-16

    申请号：ES96919001

    申请日：1996-05-02

    Applicant: QUALCOMM INC

    Inventor： ZIV NOAM A ,  PADOVANI ROBERTO ,  LEVIN JEFFREY A ,  EASTON KENNETH D

    IPC: H04L1/02 ,  H04B1/707 ,  H04B7/26 ,  H04J11/00 ,  H04J13/00 ,  H04L27/30 ,  H04Q7/20

    Abstract: An integrated search processor used in a modem for a spread spectrum communications system buffers receive samples and utilizes a time sliced transform processor operating on successive offsets from the buffer. The search processor autonomously steps through a search as configured by a microprocessor specified search parameter set, which can include the group of antennas to search over, the starting offset and width of the search window to search over, and the number of Walsh symbols to accumulate results at each offset. The search processor calculates the correlation energy at each offset, and presents a summary report of the best paths found in the search to use for demodulation element reassignment. The search is done in a linear fashion independent of the probability that a signal being searched for was transmitted at any given time.

    Synchronisation of a low power clock in a wireless communication device
    98.
    发明专利
    Synchronisation of a low power clock in a wireless communication device 未知

    公开(公告)号：AU5563599A

    公开(公告)日：2000-03-06

    申请号：AU5563599

    申请日：1999-08-13

    Applicant: QUALCOMM INC

    Inventor： BUTLER BRIAN K ,  YU NICHOLAS K ,  EASTON KENNETH D

    IPC: G06F1/08 ,  G06F1/32 ,  H03L7/00 ,  H04B1/16 ,  H04B7/26 ,  H04L7/02 ,  H04L7/033 ,  H04W52/02 ,  H04Q7/32 ,  G06F1/12

    Abstract: A method and circuit for controlling a mobile station operating in a slotted paging environment. The circuit comprises a low power clock for generating a low frequency clock signal; a clock signal generator for generating a high frequency clock signal; a synchronization logic circuit for synchronizing the low frequency clock signal to the high frequency clock signal; a frequency error estimator for measuring an estimated low frequency clock error; and a sleep controller for removing power from the clock signal generator for the corrected sleep duration value, thereby conserving power between assigned paging slots. During the awake time, the low frequency clock signal is resynchronized to the high frequency clock, thereby correcting for any frequency error in the less accurate low power clock during sleep mode.

    SYNCHRONISATION OF A LOW POWER CLOCK IN A WIRELESS COMMUNICATION DEVICE
    99.
    发明专利
    SYNCHRONISATION OF A LOW POWER CLOCK IN A WIRELESS COMMUNICATION DEVICE 未知

    公开(公告)号：CA2340446A1

    公开(公告)日：2000-02-24

    申请号：CA2340446

    申请日：1999-08-13

    Applicant: QUALCOMM INC

    Inventor： EASTON KENNETH D ,  YU NICHOLAS K ,  BUTLER BRIAN K

    IPC: G06F1/08 ,  G06F1/32 ,  H03L7/00 ,  H04B1/16 ,  H04B7/26 ,  H04L7/02 ,  H04L7/033 ,  H04W52/02 ,  H04Q7/32 ,  G06F1/12

    Abstract: A method and circuit for controlling a mobile station operating in a slotted paging environment. The circuit comprises a low power clock for generating a low frequency clock signal; a clock signal generator for generating a high frequency clock signal; a synchronization logic circuit for synchronizing th e low frequency clock signal to the high frequency clock signal; a frequency error estimator for measuring an estimated low frequency clock error; and a sleep controller for removing power from the clock signal generator for the corrected sleep duration value, thereby conserving power between assigned paging slots. During the awake time, the low frequency clock signal is resynchronized to the high frequency clock, thereby correcting for any frequency error in the less accurate low power clock during sleep mode.

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