公开(公告)号：JPH04251921A

公开(公告)日：1992-09-08

申请号：JP131691

申请日：1991-01-10

Applicant: SONY CORP

Inventor： SATO JUNICHI ,  HASEGAWA TOSHIAKI

IPC: H01L21/205 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065

Abstract: PURPOSE:To prevent cross-contamination between chambers by connecting a plurality of vacuum pumps in different vacuum degrees to a wafer transfer chambers. CONSTITUTION:In the case of executing low temperature etching, the inside of wafer transfer chamber 1 is evacuated to a high vacuum condition of 10 Torr or higher with a turbo molecular pump 12. Thereafter, a gate valve 2 is opened and a wafer 8 is then carried into a low temperature etching chamber 3A with a wafer transfer arm 9. In the case of conducting the heat processing and ashing to the wafer 8 having completed the low temperature etching process in order to prevent dewing, the wafer transfer chamber 1 is evacuated with a booster pump 13 before the wafer 8 is transferred thereto from the heat processing chamber 3B. Moreover, the nitrogen gas is supplied thereto from a dry N2 bleed apparatus via a supply pipe 14. When the pressure in the wafer transfer chamber 1 reaches 10 Torr, the gate valve 2 is opened and the wafer 8 is moved to the side of wafer transfer chamber 1.

公开(公告)号：JPH04142063A

公开(公告)日：1992-05-15

申请号：JP26310890

申请日：1990-10-02

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI ,  KADOMURA SHINGO

IPC: H01L21/3205 ,  H01L21/768

Abstract: PURPOSE:To obtain a stable deposition rate and to ensure and enhance selectivity by a method wherein an etching gas is supplied in depositing a metal or the etching gas is supplied repeatedly and alternately with the deposition operation. CONSTITUTION:An RF is applied to a plasma generation chamber 11 from an RF power supply through an upper-part electrode 14 and a lower-part electrode 15 via an RF application matching box 12. A plasma is introduced into a reaction chamber 13 installed separately form the plasma generation chamber 11. The plasma is transported to the reaction chamber 13; it is reacted. Consequently, a source gas used to deposit W on a wafer 1 supported by a wafer susceptor 16 is mixed with an etching gas by F radicals. Thereby, a concurrent reaction by the deposition of W and by an etching operation is caused. The W can be buried selectively without depending on an opening area even in the wafer which has a large opening area and a small opening area. Thereby, it is possible to prevent selectivity from being broken.

公开(公告)号：JPH04142062A

公开(公告)日：1992-05-15

申请号：JP26451990

申请日：1990-10-02

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI ,  SATO JUNICHI

IPC: H01L21/3205 ,  H01L21/768

Abstract: PURPOSE:To make the coverage of an upper-layer interconnection formed in a posterior process good by a method wherein blanket tungsten is deposited on an insulating film and inside an opening part, it is etched back and, after that, an intermediate layer is etched. CONSTITUTION:A titanium film 12 as an intermediate layer is formed on an layer insulating film 11 deposited on a silicon substrate 10 and composed of SiO2. A contact hole 13 is made; a Ti/TiN film 14 is formed as a close contact layer. Then, a blanket tungsten film 15 is formed. The blanket tungsten film 15 is etched by a first-stage etching operation; by a second-stage etching operation, the titanium film 12 is revealed so as to obtain the etching ratio of titanium to tungsten at Ti>W. As a result, a tungsten plug 15A is formed. Thereby, an upper-layer interconnection whose coverage is good can be formed.

公开(公告)号：JPH043926A

公开(公告)日：1992-01-08

申请号：JP10478790

申请日：1990-04-20

Applicant: SONY CORP

Inventor： SATO JUNICHI ,  KIYOTA HISAHARU ,  HASEGAWA TOSHIAKI

IPC: C23C16/06 ,  C23C16/44 ,  C23C16/511 ,  H01L21/28 ,  H01L21/285

Abstract: PURPOSE:To prevent the peeling of a metallic layer at a time when the high melting-point metallic layer is formed to a substrate by forming an adhesive layer so that the whole outer circumferential section of the substrate is extruded from a substrate base plate and also forming an adhesion layer around a second main surface. CONSTITUTION:When a substrate 1 is placed under the state, in which the whole outer circumferential section of the substrate is extruded from the outer circumference of a substrate table 2, and an adhesive layer 3 is formed, structure in which the adhesive layer is shaped on the whole surface of the substrate 1 is obtained while an adhesive layer is also formed on the rear as a second main surface 12 in the extruded section 1a of the substrate 1. A high melting- point metallic layer is formed on the whole surface on the adhesive layer 3 acquired through a blanket CVD method. Consequently, even when a high melting-point metal creeps and adheres on the rear of the substrate 1, there is the creeping and shaped adhesive layer section 3a on the rear previously, thus generating no peeling of the high melting-point metallic layer. Accordingly, the generation of the peel ing of the high melting-point metallic layer can be prevented, thus excellently shaping the high melting-point metallic layer.

公开(公告)号：JP2004363516A

公开(公告)日：2004-12-24

申请号：JP2003163384

申请日：2003-06-09

Applicant: Sony Corp ,  ソニー株式会社

Inventor： HASEGAWA TOSHIAKI

IPC: H01L21/3205 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming embedded wiring with high reliability which can suppress an increase in leakage current between the wirings or deterioration in reliability in TDDB or the like, upon forming the embedded wiring in a low dielectric constant film.
SOLUTION: This method has steps of forming a low dielectric constant film 32 to form a wiring groove in the low dielectric constant film; depositing a Cu film on the overall surface of a substrate to embed the wiring groove; removing the Cu film on the low dielectric constant film by applying CMP treatment to form Cu wiring 40 in the wiring groove; oxidizing the surface layer of the low dielectric constant film and the surface layer of the Cu wiring by applying low-pressure oxygen plasma treatment to form the oxide film and the Cu oxide film of the low dielectric constant film, respectively; applying surface treatment by using fluoric acid chemical liquid, to remove the oxide film and the Cu oxide film of the low dielectric constant film; and forming a CVD-insulating film 42 on the overall surface of the substrate by a CVD method as a Cu diffusion preventing film.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种高可靠性形成嵌入式布线的方法，其可以抑制在布线之间的漏电流的增加或者TDDB等的可靠性的劣化，在以低介电常数形成嵌入布线时 电影。 解决方案：该方法具有形成低介电常数膜32以在低介电常数膜中形成布线槽的步骤; 在基板的整个表面上沉积Cu膜以嵌入布线槽; 通过施加CMP处理去除低介电常数膜上的Cu膜，以在布线槽中形成Cu布线40; 通过施加低压氧等离子体处理来分别氧化低介电常数膜的表面层和Cu布线的表面层，以形成低介电常数膜的氧化物膜和Cu氧化物膜; 通过使用氟酸化学液进行表面处理，去除低介电常数膜的氧化膜和Cu氧化膜; 并且通过CVD法在基板的整个表面上形成CVD绝缘膜42作为Cu扩散防止膜。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2003031652A

公开(公告)日：2003-01-31

申请号：JP2001218363

申请日：2001-07-18

Applicant: Sony Corp ,  ソニー株式会社

Inventor： SHIBUKI SHUNICHI ,  HASEGAWA TOSHIAKI

IPC: H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a highly reliable wiring structure by suppressing permeation of moisture to the upper layer even if a moisture absorbing SiO
2 film is employed as an insulation film material thereby suppressing deterioration of an organic insulation film.
SOLUTION: In the semiconductor device having an insulation film structure where an organic insulation film is laid on an inorganic insulation film, the insulation film structure has a moisture absorbing first insulation film 12, a second insulation film 13 formed on the first insulation film 12 in order to reduce permeation of moisture to the upper layer, and an organic insulation film 14 formed on the second insulation film 13.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：即使使用吸湿SiO 2膜作为绝缘膜材料从而抑制有机绝缘膜的劣化，提供一种通过抑制水分渗透到上层而具有高度可靠的布线结构的半导体器件。 解决方案：在具有绝缘膜结构的半导体器件中，有机绝缘膜铺设在无机绝缘膜上，绝缘膜结构具有吸湿第一绝缘膜12，形成在第一绝缘膜12上的第二绝缘膜13 以减少水分渗透到上层，以及形成在第二绝缘膜13上的有机绝缘膜14。

公开(公告)号：JP2001044191A

公开(公告)日：2001-02-16

申请号：JP21150199

申请日：1999-07-27

Applicant: SONY CORP

Inventor： IKEDA KOICHI ,  FUKAZAWA MASANAGA ,  KITO HIDEYOSHI ,  HASEGAWA TOSHIAKI

IPC: H01L21/302 ,  C08J7/00 ,  C08J7/04 ,  C08K3/04 ,  C08L83/04 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To improve the performance of a semiconductor device, such as signal propagation delay, by reducing capacitance between interconnect layers and capacitance between interconnects while forming a silicon oxide film containing carbon on an organic insulating film. SOLUTION: A silicon oxide film 12 containing carbon is formed on an organic insulating film 11. Due to carbon present therein, the film 12 exhibits low relative permittivity while still holding the inorganic properties of a conventional silicon oxide film not containing an impurity such as carbon. Therefore, even when the insulating film having inorganic properties is formed on the film 11 having a low relative permittivity, lower relative permittivity can be achieved. Thus, a laminated insulating film 13 is interposed between interconnect layers and between interconnects, whereby capacitance between the interconnect layers and between the interconnects can be reduced, and this contributes to improving the performance of a semiconductor device, such as signal propagation delay.

公开(公告)号：JP2000349152A

公开(公告)日：2000-12-15

申请号：JP18122999

申请日：1999-06-28

Applicant: SONY CORP

Inventor： MIYATA KOJI ,  HASEGAWA TOSHIAKI ,  TAGUCHI MITSURU

IPC: H01L23/522 ,  H01L21/033 ,  H01L21/311 ,  H01L21/312 ,  H01L21/32 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a dual damascene structure where an interlayer insulating film is lessened in effective dielectric constant without forming an etching mask which is used for boring a connecting hole in the interlayer insulating film. SOLUTION: A process is provided in a manufacturing method, where an inorganic film 13 is formed on an interlayer insulating film 12 to serve as an inorganic film 13, a first opening pattern 16 used for forming a wiring groove 24 is provided to the inorganic film 13, and a second opening pattern 19 used for forming a connection hole 22 is formed partially overlapping with the first open pattern 16. Furthermore, after the connection hole 22 is bored in the interlayer insulating film 12 by the use of the etching mask 21 of the inorganic film 13, only a third opening pattern 23 where the first opening pattern 16 is transferred by etching the inorganic film 13 is only present, and a wiring groove 24 is formed on the interlayer insulating film 12 using the inorganic film 13 as an etching mask 21.

公开(公告)号：JP2000150646A

公开(公告)日：2000-05-30

申请号：JP32011498

申请日：1998-11-11

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI ,  IKEDA KOICHI

IPC: H01L21/768 ,  H01L21/283 ,  H01L21/31 ,  H01L21/312 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To prevent production of faulty embedding even when a metal film or the like is embedded in a connecting hole, by providing an anti-degassing insulating film for interrupting degassing from an organic insulating film on the inner wall of the connecting hole which is formed in an interlayer insulating film having at least an organic insulating film. SOLUTION: An organic insulating film 2 is formed in such a way that it covers wiring 1. An inorganic insulating film 3 is formed on the organic insulating film 2. In this way, an interlayer insulating film 4 comprises the organic insulating film 2 and the inorganic insulating film 3. Then a connecting hole is formed in the interlayer insulating film 4 reaching the wiring 1. Also, an anti-degassing insulating film 6 for interrupting the discharge of gas from the organic insulating film 2 is formed on the inner wall of the connecting hole 5. Further, a plug 7 is formed by embedding metal inside the connecting hole 5 and is connected to the wiring 1. Accordingly, since gas discharged from the organic insulating film 2 toward the connecting hole 5 can be blocked by the anti-degassing insulating film 6, no faulty embedding is caused.

公开(公告)号：JPH10150105A

公开(公告)日：1998-06-02

申请号：JP11465697

申请日：1997-05-02

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI ,  FUKAZAWA MASANAGA

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/312 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To accomplish the low dielectric constant of an interlayer insulating film where a buried wiring is formed. SOLUTION: A polyarylather organic low dielectric constant film, for example, having the dielectric constant lower than silicon oxide is used for the films 13 and 15, which become the etching stopper layers when a groove 16 and a connection hole 19 are formed, instead of using the conventional silicon nitride. Films 12, 14 and 18 can be formed by the copolymer of an annular fluorine compound and siloxane, for example, having the relative dielectric constant lower than the silicon oxide, can be used in place of the silicon oxide. In this case, the organic low dielectric constant films 13 and 15, which actually do not contain fluorine, function as the etching stopper layer of the organic low dielectric constant films 14 and 18 containing a relatively large quantity of fluorine.