中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

137 records (took 0.027 seconds)

    High-voltage switch with low output ripple for non-volatile floating-gate memories
    91.
    发明公开
    High-voltage switch with low output ripple for non-volatile floating-gate memories 有权
    具有在输出一个低纹波用于非易失性浮栅存储器的高压开关

    公开(公告)号：EP1724784A1

    公开(公告)日：2006-11-22

    申请号：EP05425347.1

    申请日：2005-05-20

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Ragone, Giancarlo ,  Crippa, Luca ,  Sangalli, Miriam ,  Micheloni, Rino

    IPC: G11C8/08 ,  G11C16/08 ,  H02M3/07 ,  H03K17/06

    CPC classification number: H02M3/073 ,  G11C5/145 ,  G11C8/08 ,  G11C16/08 ,  G11C16/12 ,  H02M2003/077 ,  H03K3/356104 ,  H03K17/063 ,  H03K17/6872 ,  H03K17/6874

    Abstract: A high-voltage switch (24) has a high-voltage input terminal (29), receiving a high voltage (HV), and an output terminal (31). A pass transistor (36), having a control terminal, is connected between the high-voltage input terminal (29) and the output terminal (31). The output of a voltage-multiplying circuit (40) of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit (40) is of a symmetrical type, has first and second charge-storage means (41, 42), receiving a clock signal (CK) of a periodic type, and has a first circuit branch (44, 48) and a second circuit branch (45, 49), which are symmetrical to one another and operate in phase opposition with respect to the clock signal (CK).

    Abstract translation: 的高电压开关（24）具有一个高电压输入端（29）接收高电压（HV），和输出端子（31）。 具有控制端子的导通晶体管（36），被连接在高电压输入端（29）和输出端子（31）之间。 电荷泵型的电压倍增电路（40）的输出被连接到控制终端。 电压倍增电路（40）是对称型，具有第一和第二电荷存储装置（41，42）接收周期性类型的时钟信号（CK），并具有第一电路支路（44，48 ）和第二电路支路（45，49），它们彼此对称和反相相对于所述时钟信号（CK）进行操作。

    Method of programming an electrically programmable non-volatile semiconductor memory
    94.
    发明公开
    Method of programming an electrically programmable non-volatile semiconductor memory 审中-公开
    编程电可编程非易失性半导体存储器的方法

    公开(公告)号：EP1426967A2

    公开(公告)日：2004-06-09

    申请号：EP03104383.9

    申请日：2003-11-26

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Ravasto, Roberto ,  Scommegna, Salvatrice

    IPC: G11C11/56

    CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

    Abstract: A method of programming an electrically programmable memory comprises: accessing a group of memory cells ( MC1-MCk ) of the memory to ascertain a programming state thereof ( 401,407;503,509a,513a ); applying a programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state ( 405;507a,509c,513c ); and repeating said acts of accessing and applying for the memory cells in the group whose programming state is not ascertained ( 411;509b,513b ). After the programming state of a prescribed number of memory cells in the group has been ascertained, the memory cells in the group are accessed again and the programming state of the memory cells whose programming state was previously ascertained is re-ascertained ( 413,415;515 ); at least one additional programming pulse is applied to those memory cells in the group whose programming state is not re-ascertained ( 405;507a,509c,513c ). The method guarantees that the programming state of the memory cells is ascertained in conditions that closely resembles, or are substantially identical, to the conditions in which the memory cells will be accessed in a standard read.

    Abstract translation: 一种对电可编程存储器进行编程的方法包括：访问存储器的一组存储单元（MC1-MCk）以确定其编程状态（401,407; 503,509a，513a）; 将编程脉冲施加到其编程状态未被确定为对应于期望的编程状态（405; 507a，509c，513c）的组中的那些存储器单元; 并且重复所述访问和应用编程状态未被确定的组中的存储器单元的行为（411; 509b，513b）。 在确定了该组中规定数量的存储单元的编程状态之后，再次访问该组中的存储单元，并重新确定编程状态先前确定的存储单元的编程状态（413,415; 515） ; 至少一个附加编程脉冲被施加到其编程状态未被重新确定的组中的那些存储器单元（405; 507a，509c，513c）。 该方法保证了在与标准读取中存储单元将被访问的条件非常相似或基本相同的条件下确定存储单元的编程状态。

    Method for detecting a resistive path or a predeterminted potential in non-volatile memory electronic devices
    95.
    发明公开
    Method for detecting a resistive path or a predeterminted potential in non-volatile memory electronic devices 有权
    的电子非易失性存储器装置检测的电阻路径或者预定电势的方法，

    公开(公告)号：EP1403880A1

    公开(公告)日：2004-03-31

    申请号：EP02425593.7

    申请日：2002-09-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: G11C29/00

    CPC classification number: G11C29/82 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50008 ,  G11C29/83 ,  G11C29/832

    Abstract: The invention relates to a method for pinpointing erase-failed memory cells and to a relevant integrated non-volatile memory device, of the programmable and electrically erasable type comprising a sectored array of memory cells (4) arranged in rows and columns, with at least one row-decoding circuit portion per sector (20) being supplied positive and negative voltages (Vpcx, HVNEG).
    This method becomes operative upon a negative erase algorithm issue, and comprises the following steps:

    forcing the read condition of a sector (20) that has not been completely erased;
    scanning the rows of said sector (20) to check for the presence of a spurious current indicating a failed state;
    finding the failed row and electrically isolating it for re-addressing the same to a redundant row provided in the same sector (20).

    Abstract translation: 该方法包括迫使读取条件到任何完全擦除扇区。 该部门的行进行扫描来检查当前虚假的可能存在，表明所有这一切是一个失败的国家。 流过一排寄生电流被发现，所有这一切都被电通过重新寻址的行，以相同的扇区提供一个冗余行隔离。 因此独立claimsoft被包括用于在可编程和电可擦除型的集成的非易失性存储器设备。

    Regulation method for the source voltage in a nonvolatile memory cell during programming and corresponding program circuit
    97.
    发明公开
    Regulation method for the source voltage in a nonvolatile memory cell during programming and corresponding program circuit 有权
    一种用于编程非易失性存储器单元期间调节的源极电压和相应的编程电路的方法

    公开(公告)号：EP1331644A3

    公开(公告)日：2004-02-04

    申请号：EP02019433.8

    申请日：2002-08-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Motta, Maria

    IPC: G11C16/30

    CPC classification number: G11C16/30

    Abstract: The invention relates to a method and a circuit for regulating the source terminal (S) voltage to the of a non-volatile memory cell (3) during the cell programming and/or reading phases. The method comprises a phase of locally regulating said voltage value and consists of comparing the source current (Is) of the cell array (3) with a reference current (Iref). A fraction of the source current (Is) is converted to a voltage and compared with a voltage generated from a memory cell acting as a reference and being programmed to the distribution with the highest current levels; the comparison result being used for controlling a current generator (25) to inject, into the source terminal (S), the current necessary to keep the predetermined voltage thereof at a constant value.

    Method and circuit for generating reference voltages for reading a multilevel memory cell
    100.
    发明公开
    Method and circuit for generating reference voltages for reading a multilevel memory cell 有权
    操作和电路，用于产生参考电压，用于读取的多值存储单元

    公开(公告)号：EP1253597A1

    公开(公告)日：2002-10-30

    申请号：EP01830276.0

    申请日：2001-04-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni

    IPC: G11C11/56 ,  G11C5/14

    CPC classification number: G11C11/56 ,  G11C5/147 ,  G11C11/5621 ,  G11C11/5642 ,  G11C2211/5634

    Abstract: The circuit for generating reference voltages for reading a multilevel memory cell includes the following: a first memory cell (236) and a second memory cell (236) respectively having a first reference programming level and a second reference programming level; a first reference circuit (46) and a second reference circuit (47) respectively connected to said first and said second memory cells (236) and having respective output terminals (60) which respectively supply a first reference voltage (VR1) and a second reference voltage (VRN-1); and a voltage divider (48) having a first connection node (42.1) and a second connection node (42.N-1) respectively connected to the output terminals (60) of the first reference circuit (46) and of the second reference circuit (47) to receive, respectively, the first reference voltage (VR1) and the second reference voltage (VRN-1), and a plurality of intermediate nodes (42.2,..., 42.N-2) supplying respective third reference voltages (VR2,..., VRN-2) at equal distances apart.

    Abstract translation: 用于产生参考电压，用于读取多电平存储器单元中的电路包括以下内容：分别具有第一参考电平的编程和第二参考电平编程第一存储器单元（236）和一个第二存储单元（236）; 其分别提供第一参考电压的第一参考电路（46）和第二参考电路（47）分别连接到所述第一和所述第二存储器单元（236）和具有respectivement输出端子（60）（VR1）和第二参考 电压（VRN-1）; 并分别连接到所述第一参考电路（46）的输出端子（60）的分压器（48），其具有第一连接节点（42.1）和第二连接节点（42.n-1）和第二参考电路的 （47），以分别接收所述第一参考电压（VR1）和第二参考电压（VRN-1），和中间节点的多个（42.2，...，42.n-2）供给respectivement第三参考电压 （VR2，...，VRN-2）相等的距离隔开。

Patent Agency Ranking