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    Semiconductor package apparatus and method of manufacturing the same
    91.
    发明专利
    Semiconductor package apparatus and method of manufacturing the same 审中-公开
    半导体封装装置及其制造方法

    公开(公告)号：JP2009038375A

    公开(公告)日：2009-02-19

    申请号：JP2008196736

    申请日：2008-07-30

    Applicant: Samsung Electronics Co Ltd ,  三星電子株式会社Samsung Electronics Co.,Ltd.

    Inventor： SHIN DONG-KIL ,  PARK SANGOOK

    IPC: H01L23/50 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18

    CPC classification number: H05K3/3426 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K2201/10477 ,  H05K2201/10689 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package apparatus and a method of manufacturing the same. SOLUTION: The semiconductor package apparatus includes: semiconductor chips comprising active and inactive surfaces and protected by a packing portion; a substrate on which the semiconductor chips are installed; leads comprising front portions electrically coupled to the active surfaces of the semiconductor chips and rear portions extending substantially to the substrate; and bonding materials bonded between ends of the rear portions of the leads and the substrate so as to electrically couple the leads to the substrate. A part including the ends of the rear portions of the leads may stand on the substrate. Thus, the reliability of the electric coupling of bonded pats can be improved, and a wetting characteristic of solder can be improved during surface installation. Also, semiconductor package apparatuses having similar attributes can easily be multilayered, and a foot print of the semiconductor package apparatus can be reduced to allow high-density installation, and shapes of the bonding materials (solder) can be controlled to optimize the bonding strength of the leads and the quantity of the bonding materials. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 解决的问题：提供一种半导体封装装置及其制造方法。 解决方案：半导体封装装置包括：包含有源和非活性表面并被封装部分保护的半导体芯片; 其上安装有半导体芯片的基板; 引线包括电耦合到半导体芯片的有源表面的前部和基本上延伸到衬底的后部; 以及接合在引线的后部的端部与基板之间的接合材料，以将引线电耦合到基板。 包括引线的后部的端部的部分可以位于基板上。 因此，可以提高粘合片的电耦合的可靠性，并且可以在表面安装期间改善焊料的润湿特性。 此外，具有相似属性的半导体封装装置可以容易地多层化，并且可以减少半导体封装装置的脚印以允许高密度安装，并且可以控制接合材料（焊料）的形状以优化粘合强度 引线和接合材料的数量。 版权所有（C）2009，JPO＆INPIT

    Stack memory and its manufacturing method
    94.
    发明专利
    Stack memory and its manufacturing method 审中-公开
    堆叠存储器及其制造方法

    公开(公告)号：JP2005051143A

    公开(公告)日：2005-02-24

    申请号：JP2003283598

    申请日：2003-07-31

    Applicant: Nec Toshiba Space Systems Ltd ,  Nec東芝スペースシステム株式会社

    Inventor： EBIHARA NOBUAKI ,  SUZUKI NAOSHI

    IPC: H01L25/18 ,  H01L25/10 ,  H01L25/11 ,  H05K1/14 ,  H05K3/32 ,  H05K3/34

    CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/144 ,  H05K1/145 ,  H05K3/321 ,  H05K3/3421 ,  H05K2201/0397 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10969 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a stack memory having excellent heat-dissipating properties and heat-insulating properties and being used even in an apparatus utilized under a severe use environment such as the apparatus for an artificial satellite. SOLUTION: Leads 7 formed to TSOPs 1 are joined with pads 11 for interposer substrates 2 by a thermosetting type conductive resin 5. The TSOPs 1 are loaded on the substrates 2 by joining sections other than the leads 7 for the TSOPs 1 with ground layers 9 formed to the interposers 2 by the thermosetting type conductive resin 4. The interposer substrates 2 on which the TSOPs 1 are loaded are arranged so that the TSOPs 1 are positioned on lower sides, and eight interposer substrates 2 are laminated. The interposer substrates 2 adjacent in the vertical direction are connected by joining the leads 8 for the interposer substrates 2 at upper stages with the pads 11 formed to rears of the substrates 2 at lower stages by the thermosetting type conductive resin 6. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供具有优异的散热特性和隔热性能的堆叠存储器，并且即使在诸如用于人造卫星的装置的严酷使用环境下使用的装置中也是如此。 解决方案：形成于TSOP 1的引线7通过热固型导电树脂5与用于插入器基板2的焊盘11连接。通过将除了用于TSOP 1的引线7之外的部分接合，将TSOP1加载到基板2上， 通过热固性型导电树脂4形成在内插件2上的接地层9.将TSOP 1载置在其上的插入物基板2配置成使得TSOP1位于下侧，并且层叠8个插入基板2。 在垂直方向上相邻的插入器基板2通过在上部阶段连接用于插入器基板2的引线8来连接，其中焊盘11通过热固性型导电树脂6在较低的阶段形成为衬底2的回转。 （C）2005，JPO＆NCIPI

    集成模块、集成系统板和电子设备
    97.
    发明申请
    集成模块、集成系统板和电子设备 审中-公开

    公开(公告)号：WO2013107305A1

    公开(公告)日：2013-07-25

    申请号：PCT/CN2013/070094

    申请日：2013-01-06

    Applicant: 华为终端有限公司

    Inventor： 丁海幸 ,  谢桂福

    IPC: H01L23/498 ,  H05K1/18

    CPC classification number: H05K1/181 ,  H05K1/0268 ,  H05K1/0295 ,  H05K1/113 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/09954 ,  H05K2201/10477 ,  H05K2203/162

    Abstract: 提供一种集成模块、集成系统板和电子设备。集成模块包括印刷电路板（PCB）（10）和模块器件（20），其中，所述模块器件（20）贴装在所述PCB（10）上。所述PCB（10）的正面的四周设置一组正面引脚焊盘（11），且所述正面引脚焊盘（11）位于所述模块器件（20）的贴装位置周围，所述PCB（10）的底面的四周设置一组底面引脚焊盘（12）；设置所述正面引脚焊盘（11）的位置与设置所述底面引脚焊盘（12）的位置互为对称，所述正面引脚焊盘（11）与所述底面引脚焊盘（12）的网络属性相同。集成系统板包括集成模块和主板，所述集成模块包括印刷电路板（10）和模块器件（20）。电子设备包括上述集成系统板。本实施例无需增加额外的测试线路，提高了测试集成模块的便利性。

    REMOVABLE PACKAGE UNDERSIDE DEVICE ATTACH
    99.
    发明申请
    REMOVABLE PACKAGE UNDERSIDE DEVICE ATTACH 审中-公开
    可拆卸包装下面的设备附件

    公开(公告)号：WO2010078021A3

    公开(公告)日：2010-09-16

    申请号：PCT/US2009068440

    申请日：2009-12-17

    Applicant: INTEL CORP ,  DESHPANDE ANAND ,  NATARAJAN VENKAT ,  KABADI ASHOK ,  KINI VITTAL

    Inventor： DESHPANDE ANAND ,  NATARAJAN VENKAT ,  KABADI ASHOK ,  KINI VITTAL

    IPC: H01L23/12 ,  H01L23/48

    CPC classification number: H01L23/3677 ,  H01L23/40 ,  H01L23/427 ,  H01L2224/73253 ,  H05K1/0203 ,  H05K1/141 ,  H05K3/325 ,  H05K2201/10159 ,  H05K2201/10325 ,  H05K2201/10477 ,  H05K2201/10719

    Abstract: In some embodiments, a stacked package assembly may include a first socket defining an interior cavity, a first semiconductor device coupled to the first socket, a second socket positioned within the interior cavity of the first socket, and a second semiconductor device removably coupled to the second socket within the cavity of the first socket. The second socket may be positioned between the first semiconductor device and the second semiconductor device and provide an electrical connection between the first semiconductor device and the second semiconductor device. Other embodiments are disclosed and claimed.

    Abstract translation: 在一些实施例中，堆叠封装组件可以包括限定内部空腔的第一插座，耦合到第一插座的第一半导体器件，位于第一插座的内部空腔内的第二插座以及可移除地耦合到第一插座的第二半导体器件 第二插座在第一插座的空腔内。 第二插座可以位于第一半导体器件和第二半导体器件之间并且提供第一半导体器件和第二半导体器件之间的电连接。 其他实施例被公开和要求保护。

    A METHOD FOR MANUFACTURING AN ELECTRONIC ASSEMBLY; AN ELECTRONIC ASSEMBLY, A COVER AND A SUBSTRATE
    100.
    发明申请
    A METHOD FOR MANUFACTURING AN ELECTRONIC ASSEMBLY; AN ELECTRONIC ASSEMBLY, A COVER AND A SUBSTRATE 审中-公开
    一种制造电子组件的方法; 电子组件，盖子和基板

    公开(公告)号：WO2007119206A2

    公开(公告)日：2007-10-25

    申请号：PCT/IB2007/051297

    申请日：2007-04-11

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  WEEKAMP, Johannes, W. ,  SLOB, Cornelis ,  SCHEER, Jacob, M. ,  VAN STRATEN, Freerk, E.

    Inventor： WEEKAMP, Johannes, W. ,  SLOB, Cornelis ,  SCHEER, Jacob, M. ,  VAN STRATEN, Freerk, E.

    IPC: B81C1/00

    CPC classification number: B81C1/00833 ,  B81C1/00269 ,  B81C2203/035 ,  H05K3/341 ,  H05K2201/10371 ,  H05K2201/10477 ,  H05K2203/1147 ,  Y02P70/613 ,  Y10T29/49117

    Abstract: The present invention relates to a method for manufacturing an electronic assembly (50) comprising an electronic component, a cavity and a substrate which method comprises; -providing an electronic component (10) having a first pattern with a substantially closed configuration; -providing a cover (18) on a surface of the electronic component, which cover together with said surface defines a cavity (20), the closed configuration of the first pattern substantially enclosing the cover at said surface; -providing a substrate (30) having a second pattern with a substantially closed configuration, which closed configuration at least partially corresponds to the closed configuration of the first pattern and comprises a solder pad; -disposing solder material at the solder pad; -positioning the electronic component and the substrate so as to align both the substantially closed configurations of the first and second pattern, while the substrate supports a top surface (28) of the cover; -reflow-soldering the solder material, therewith providing a soldered connection (52) between the first and second pattern. Furthermore the present invention relates to an electronic assembly (50), a cover (18) and a substrate (30).

    Abstract translation: 本发明涉及一种用于制造电子组件（50）的方法，所述电子组件（50）包括电子部件，空腔和基板，所述方法包括： - 提供具有基本上封闭构造的第一图案的电子部件（10） - 提供与所述表面一起覆盖的所述电子部件的表面上的盖子（18）限定空腔（20），所述第一图案的所述封闭构造基本上在所述表面上包围所述盖子; - 提供具有基本封闭构造的第二图案的衬底（30），该封闭构造至少部分对应于第一图案的封闭构造，并且包括焊盘; - 在焊料垫上涂抹焊料; - 定位所述电子部件和所述基板，以便在所述基板支撑所述盖的顶表面（28）的同时对准所述第一和第二图案的所述基本上封闭的构造; - 回流焊接焊料材料，从而在第一和第二图案之间提供焊接连接（52）。 此外，本发明涉及电子组件（50），盖（18）和基板（30）。

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