公开(公告)号：WO2021118869A1

公开(公告)日：2021-06-17

申请号：PCT/US2020/063215

申请日：2020-12-04

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： RAMAN, Madhusudan ,  DUNOYER, Julien G. ,  ABDALLAH, Nizar

IPC: G06F30/27 ,  G06F30/3312 ,  H01L21/66 ,  G06F119/12

Abstract: A method for integrated circuit design with delay verification includes storing configuration files for a slew-rate Machine Learning (ML) model, a net-delay ML model and a cell-delay ML model. A user design is received, slew-rate feature values, net-delay feature values and cell-delay feature values are extracted from the user design, the configuration files are loaded to form inference cores, and operations of the slew-rate inference core are performed to calculate predicted slew-rate values that are sent to ML design tools. Operations of the net-delay inference core are performed to calculate predicted net-delay values that are sent to the ML design tools. Operations of the cell-delay inference core are performed to generate predicted cell-delay values that are sent to the ML design tools. The user design is iterated until a user design is obtained that is free of timing violations.

公开(公告)号：WO2021118637A1

公开(公告)日：2021-06-17

申请号：PCT/US2020/037630

申请日：2020-06-12

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： WILLIAMSON, Michael R.

IPC: H03K23/68 ,  G06F1/03 ,  G06F13/42

Abstract: A circuit for transferring a n-bit phase value between circuits includes a system clock input, a n-bit phase value generator coupled to the system clock input generating a phase value output, and an edge output indicating the phase output value is valid, a latching clock delay circuit having an input coupled to the system clock input, an input coupled to the edge output, a variable phase delay circuit coupled to the phase value output, a delay adder having a first input coupled to the phase value output, a second input coupled to a delay offset signal, and an output coupled to the control input of the variable phase delay circuit, and a phase flip-flop having a data input coupled to the output of the variable phase delay circuit, a clock input coupled to a latching clock output of the variable output clock delay circuit and a Phase Out output.

公开(公告)号：WO2021071552A1

公开(公告)日：2021-04-15

申请号：PCT/US2020/028261

申请日：2020-04-15

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： KLEIN, Matthias ,  ZAKRZEWSKI, Andreas ,  GRUENWALD, Richard

IPC: B81C1/00

Abstract: A packaged electronic die having a micro-cavity and a method for forming a packaged electronic die. The packaged electronic die includes a photoresist frame secured to the electronic die and extending completely around the device. The photoresist frame is further secured to a first major surface of a substrate so as to form an enclosure around the device. Encapsulant material extends over the electronic die and around the sides of the electronic die. The encapsulant material is in contact with the first major surface of the substrate around the entire periphery of the electronic die so as to form a seal around the electronic die.

公开(公告)号：WO2021061170A1

公开(公告)日：2021-04-01

申请号：PCT/US2019/061469

申请日：2019-11-14

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： BRITTON, Barry ,  JOHNSON, Phillip ,  SCHADT, John ,  ONIMUS, David

IPC: H03K3/013 ,  H03K3/037 ,  H03K3/356

Abstract: An SEU immune flip-flop includes a master stage data latch, being transparent in response to a clock signal first state and being latched in response to a clock signal second state; a slave stage data latch; and a scan slave latch having an input coupled to the slave stage data latch scan output, being transparent in response to the clock signal second state and being latched in response to the clock signal first state. The slave stage data latch includes a switched inverter disabled when the slave latch is in a transparent state and enabled when the slave latch is in a latched state having a time delay longer than an SEU time period.

公开(公告)号：WO2021040762A1

公开(公告)日：2021-03-04

申请号：PCT/US2019/061437

申请日：2019-11-14

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： MOK, Winston ,  GORSHE, Steven Scott

IPC: H04L29/06 ,  H04L12/00

Abstract: A method for extracting path overhead (POH) data blocks from a data stream in a 64B/66B-block communication link, the method includes receiving at a sink node a data stream in a 64B/66B-block communication link, detecting within the data stream at a PCS sublayer a micro-packet starting with an /S/ control block, including K POH data blocks, and ending with a /T/ control block, extracting the micro-packet from the data stream, and extracting the POH data blocks from the micro-packet.

公开(公告)号：WO2021015823A1

公开(公告)日：2021-01-28

申请号：PCT/US2020/021289

申请日：2020-03-05

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： GRAUMANN, Peter John Waldemar

IPC: G06F11/10

Abstract: A method and apparatus for decoding are disclosed. The method includes receiving a first Forward Error Correction (FEC) block of read values, starting a hard-decode process in which a number of check node failures is identified and, during the hard-decode process comparing the identified number of check node failures to a decode threshold. When the identified number of check node failures is not greater than the decode threshold the hard-decode process is continued. When the identified number of check node failures is greater than the decode threshold, the method includes: stopping the hard-decode process prior to completion of the hard-decode process; generating output indicating that additional reads are required; receiving one or more additional FEC blocks of read values, mapping the first FEC block of read values and the additional FEC blocks of read values into soft-input values; and performing a soft-decode process on the soft-input values.

公开(公告)号：WO2020247013A1

公开(公告)日：2020-12-10

申请号：PCT/US2019/061857

申请日：2019-11-15

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： GENDRON-HANSEN, Amaury ,  SDRULLA, Dumitru

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/12 ,  H01L21/336

Abstract: A high-voltage termination for a semiconductor device includes a substrate, an implanted device region, a shallow trench adjacent to the implanted device region, and a doped extension region between the implanted device region and a first edge of the shallow trench adjacent to the implanted device region. A junction termination extension region is formed in the shallow trench contacting the extension region and extending past a second edge of the shallow trench opposite the implanted device region. An insulating layer is formed over at least a portion of the extension region and over the junction termination extension region. A metal layer is formed over the insulating layer.

公开(公告)号：WO2015200092A3

公开(公告)日：2015-12-30

申请号：PCT/US2015/036455

申请日：2015-06-18

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： MEDNIK, Alexander ,  TIRUMALA, Rohit ,  TAN, Mark ,  KRUGLY, Simon

IPC: H02M3/1584 ,  H02M3/156 ,  H02M3/158

Abstract: A comparator sense input is disconnected from a current sense resistor for the duration of a switching transition in an adjacent channel(s). Instead, the sense input receives a signal of the magnitude and the slew rate sampled prior to the transition.

公开(公告)号：WO1997044904A1

公开(公告)日：1997-11-27

申请号：PCT/US1997008185

申请日：1997-05-21

Applicant: MICROCHIP TECHNOLOGY, INC.

Inventor： MICROCHIP TECHNOLOGY, INC. ,  HULL, Richard, L. ,  BINGHAM, Gregory

IPC: H03L07/00

CPC classification number: H03K17/164 ,  G06F1/08 ,  G06F15/7814 ,  H03K3/0231 ,  Y02D10/12 ,  Y02D10/13

Abstract: A microcontroller circuit (10) includes an oscillator (14) receiving frequency trimming data (28) from a memory (16) under control of a microcontroller logic (12). The microcontroller logic (12) permits a user to alter the trimming data and to select through an oscillator logic (20) either the oscillator (14) or an external oscillator source (34) as a system clock (32).

Abstract translation: 微控制器电路（10）包括在微控制器逻辑（12）的控制下从存储器（16）接收频率修整数据（28）的振荡器（14）。 微控制器逻辑（12）允许用户改变修整数据并通过振荡器逻辑（20）选择振荡器（14）或外部振荡器源（34）作为系统时钟（32）。

公开(公告)号：WO1996004680A1

公开(公告)日：1996-02-15

申请号：PCT/US1995009968

申请日：1995-07-21

Applicant: MICROCHIP TECHNOLOGY, INC.

Inventor： MICROCHIP TECHNOLOGY, INC. ,  JACKSON, Daniel, J.

IPC: H01L21/44

CPC classification number: H01L21/76819 ,  Y10S438/978

Abstract: This disclosure is directed to a method of producing a smooth surface for a dielectric coating (34) that is located above the surface of semiconductor substrate (10) containing doped regions (26, 32, 34) of a semiconductor device. Sharp edges (40, 42) formed in the dielectric coating (34) during certain semiconductor processing steps are removed using a deposition process to deposit a separate insulating layer (48) on the dielectric coating (34) containing the sharp edges (40, 42) followed by an annealing operation and the subsequent removal of the separate insulating layer (48) to permit the subsequent formation of electrodes (50, 52, 54) on a smooth surface of the dielectric coating (34).

Abstract translation: 本公开涉及一种制造用于介电涂层（34）的平滑表面的方法，所述介电涂层位于包含半导体器件的掺杂区域（26,32,34）的半导体衬底（10）的表面上方。 在某些半导体处理步骤中形成在电介质涂层（34）中的尖锐边缘（40,42）使用沉积工艺去除，以在包含尖锐边缘（40,42）的电介质涂层（34）上沉积单独的绝缘层（48） ），然后进行退火操作，随后移除单独的绝缘层（48）以允许随后在电介质涂层（34）的光滑表面上形成电极（50,52,54）。