公开(公告)号：KR1020050059420A

公开(公告)日：2005-06-20

申请号：KR1020040100936

申请日：2004-12-03

Applicant: 삼성전자주식회사

Inventor： 최재광 ,  이재동 ,  홍창기

IPC: H01L21/304

CPC classification number: H01L21/3212 ,  C09G1/02 ,  C09K3/1463 ,  H01L21/7684

Abstract: 본 발명의 전형적인 실시예는 폴리실리콘층의 화학기계적연마를 포함하는 공정에 사용할 수 있는 새로운 슬러리 조성물을 제공한다. 슬러리 조성물은 실리콘 산화물 및 실리콘 질화물에 대해 폴리실리콘 제거 속도를 감소하고 연마된 표면의 평탄도를 개선하기 위해서 노출된 폴리실리콘 표면 상에 패시베이션층을 선택적으로 형성할 수 있는 하나 또는 그 이상의 비이온성 폴리머 계면활성제를 포함한다. 전형적인 계면활성제는 에틸렌 산화물(EO)-프로필렌 산화물(PO) 블록 폴리머로 이루어진 알킬 및 아릴 알콜을 포함하고, 상기 계면활성제는 보다 작은 양이면 효과적이지만 5Wt%까지의 양으로 슬러리 조성물에 존재할 수 있다. 다른 슬러리 첨가제는 점도 조절제, pH 조절제, 분산제, 칠레이팅제, 및 아민 또는 이민 계면활성제를 포함하여 실리콘 질화물 및 실리콘 산화물의 상대적인 제거 속도를 조절한다.

公开(公告)号：KR1020040089150A

公开(公告)日：2004-10-21

申请号：KR1020030022764

申请日：2003-04-10

Applicant: 삼성전자주식회사

Inventor： 이종원 ,  홍창기 ,  김호영

IPC: H01L21/304

CPC classification number: B24B37/26 ,  B24B41/04

Abstract: PURPOSE: A CVD apparatus for fabricating an IC is provided to control a polishing degree of each part of a wafer by increasing or reducing a standby period of pad strips on the wafer. CONSTITUTION: A plate is used for fixing a semiconductor substrate. A polishing pad(320) includes a plurality of pad strips and is used for pressing the semiconductor substrate. A rotation unit(380) is used for rotating the polishing pad. A migration unit moves straightly a part of the pad strips. The polishing pad is formed with a circular shape. Each pad strip has a shape of a fan. The migration unit includes a motor(370), a screw(360) rotated by the motor, and a rod migrated by the rotation of the screw.

Abstract translation: 目的：提供一种用于制造IC的CVD装置，通过增加或减少晶片上的焊盘条的待机周期来控制晶片的每个部分的抛光度。 构成：用于固定半导体衬底的板。 抛光垫（320）包括多个垫条，并用于按压半导体基板。 旋转单元（380）用于旋转抛光垫。 迁移单元直接移动一部分垫片条。 抛光垫形成圆形。 每个垫条具有风扇的形状。 迁移单元包括马达（370），由马达旋转的螺钉（360）和通过螺杆旋转而移动的杆。

公开(公告)号：KR1020040036020A

公开(公告)日：2004-04-30

申请号：KR1020020064772

申请日：2002-10-23

Applicant: 삼성전자주식회사

Inventor： 박영래 ,  박정헌 ,  홍창기

IPC: H01L21/302

Abstract: PURPOSE: A planarization method of a semiconductor device using a CMP(Chemical Mechanical Polishing) process is provided to be capable of uniformly polishing an insulating layer formed on the first and second lower patterns and minimizing the damage of the first and second lower patterns. CONSTITUTION: A semiconductor substrate is prepared. At this time, the semiconductor substrate includes the first lower patterns(106) having the first height(Ha) and the second lower patterns(106a) having the second height(Hb). An insulating layer is formed on the entire surface of the resultant structure. A planarization process is performed on the resultant structure by using a CMP apparatus having an etch end point detector until the upper surfaces of the second lower patterns are exposed.

Abstract translation: 目的：提供使用CMP（化学机械抛光）工艺的半导体器件的平面化方法，以能够均匀地抛光形成在第一和第二下部图案上的绝缘层，并且使第一和第二下部图案的损伤最小化。 构成：制备半导体衬底。 此时，半导体衬底包括具有第一高度（Ha）的第一下部图案（106）和具有第二高度（Hb）的第二下部图案（106a）。 在所得结构的整个表面上形成绝缘层。 通过使用具有蚀刻终点检测器的CMP设备对所得到的结构进行平坦化处理，直到第二下部图案的上表面露出。

公开(公告)号：KR1020040017881A

公开(公告)日：2004-03-02

申请号：KR1020020049803

申请日：2002-08-22

Applicant: 삼성전자주식회사

Inventor： 박영래 ,  박정헌 ,  홍창기

IPC: H01L27/108

Abstract: PURPOSE: A method for forming a capacitor of a semiconductor device is provided to be capable of simplifying the forming process. CONSTITUTION: A mold insulating layer(107) and a hard mask(108) are sequentially formed at the upper portion of a semiconductor substrate(101). A plurality of holes(109a) are formed on the resultant structure by sequentially patterning the hard mask and the mold insulating layer. An storage node layer(110) is formed along the entire surface of the resultant structure. Then, a capping insulating layer(111) is formed at the upper portion of the storage node layer for completely filling the holes. A plurality of storage nodes and capping insulating patterns are formed at the inner portions of the holes by carrying out a planarization process on the resultant structure using a one-step CMP(Chemical Mechanical Polishing) process.

Abstract translation: 目的：提供一种用于形成半导体器件的电容器的方法，以能够简化形成过程。 构成：在半导体基板（101）的上部依次形成模具绝缘层（107）和硬掩模（108）。 通过对硬掩模和模具绝缘层进行顺序构图，在所得结构上形成多个孔（109a）。 沿所得结构的整个表面形成存储节点层（110）。 然后，在存储节点层的上部形成封盖绝缘层（111），以完全填充孔。 通过使用一步CMP（化学机械抛光）工艺对所得结构进行平坦化处理，在孔的内部形成多个存储节点和封盖绝缘图案。

公开(公告)号：KR1020040004794A

公开(公告)日：2004-01-16

申请号：KR1020020038823

申请日：2002-07-05

Applicant: 삼성전자주식회사

Inventor： 한용필 ,  홍창기 ,  박준상 ,  김호영

IPC: H01L21/304

Abstract: PURPOSE: A slurry supply apparatus used for a CMP(Chemical Mechanical Polishing) process is provided to be capable of preventing micro scratch from being generated at a wafer due to the large grains of slurry. CONSTITUTION: A slurry supply apparatus is provided with a supply pipe(200) for supplying slurry and a module(100) connected with the supply pipe for crushing the slurry flowed from the supply pipe. The module includes the first body part(120) having a through hole connected with the supply pipe, the second body part(130) located at the lower portion of the first body part, and a motor(150) for rotating the second body part. At this time, a gap(122) is formed between the first and second body part. Preferably, the module further includes a housing for enclosing the first and second body part. The housing includes a jet port for supplying the slurry flowed from the gap to a polishing pad.

Abstract translation: 目的：提供用于CMP（化学机械抛光）方法的浆料供应装置，以能够防止由于大量浆料而在晶片上产生微刮痕。 构成：浆料供给装置设置有用于供给浆料的供给管（200）和与供给管连接的用于粉碎从供给管流出的浆料的模块（100）。 模块包括具有与供给管连接的通孔的第一主体部分（120），位于第一主体部分下部的第二主体部分（130）和用于使第二主体部分 。 此时，在第一和第二主体部分之间形成间隙（122）。 优选地，模块还包括用于封闭第一和第二主体部分的壳体。 壳体包括用于将从间隙流动的浆料供应到抛光垫的喷射口。

公开(公告)号：KR100333057B1

公开(公告)日：2002-04-22

申请号：KR1020000039609

申请日：2000-07-11

Applicant: 삼성전자주식회사

Inventor： 부재필 ,  탁수영 ,  김광복 ,  김경현 ,  홍창기

IPC: H01L27/115

Abstract: 플로팅 게이트를 스톱층으로 이용하여 CMP 공정을 통해 소자격리 영역의 절연막과 플로팅 게이트간의 단차를 감소시키는데 적당한 서로 다른 두께를 갖는 2가지 이상의 터널 절연막을 갖는 비휘발성 메모리 소자의 제조방법에 관한 것으로, 셀 트랜지스터와 외부전원 인가 및 주변회로 동작을 위한 트랜지스터를 갖는 소자에 있어서, 반도체 기판상에 서로 다른 두께를 갖는 2가지 이상의 터널 절연막과, 일정 간격을 갖는 도전층 그리고 제 1 절연막을 차례로 형성하는 제 1 단계와; 상기 형성된 결과물을 선택적으로 소정 깊이 식각 제거하여 트렌치를 형성하고, 상기 트렌치를 포함한 전체상부에 제 2 절연막을 증착하는 제 2 단계와; 상기 제 2 절연막이 상기 트렌치에만 남도록 하여 소자격리 영역을 형성하는 제 3 단계와; 상기 제 1 절연막을 제거한 후, 상기 도전층을 스톱층으로 이용하여 제 2 절연막을 선택적으로 제거하는 제 4 단계를 포함하여 이루어짐을 특징으로 한다.

公开(公告)号：KR1020020015160A

公开(公告)日：2002-02-27

申请号：KR1020000048326

申请日：2000-08-21

Applicant: 삼성전자주식회사

Inventor： 이선웅 ,  부재필 ,  김경현 ,  홍창기

IPC: H01L21/336

CPC classification number: H01L21/823468 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823443

Abstract: PURPOSE: A method for forming a metal-oxide-semiconductor(MOS) transistor using a selective silicide process is provided to control a defect inside a silicon substrate in a silicide process by selectively forming a silicide layer only on a gate polysilicon layer, and to form a relatively thin interlayer dielectric covering the silicide layer by forming the silicide layer after an insulation layer is formed. CONSTITUTION: A gate insulation layer(410) and a gate polysilicon layer(420) are sequentially formed on the silicon substrate(400). A gate spacer(430) is formed on the sidewall of the gate insulation layer and the gate polysilicon layer. An impurity ion implantation process and a diffusion process are performed to form a source/drain region(440) in the substrate by using the gate spacer and the gate polysilicon layer as a mask. An etch stop layer(450) is formed to cover the source/drain region, the gate spacer and the gate polysilicon layer. An insulation layer(460) covering the etch stop layer is formed. The insulation layer is planarized to expose the etch stop layer on the gate polysilicon layer. Parts of the exposed etch stop layer and the gate spacer are etched to expose the upper surface and upper side surface of the gate polysilicon layer. The silicide layer(480) is selectively formed on the exposed portion of the gate polysilicon layer.

Abstract translation: 目的：提供一种使用选择性硅化物工艺形成金属氧化物半导体（MOS）晶体管的方法，以通过在栅极多晶硅层上选择性地形成硅化物层来控制硅化物工艺中的硅衬底内的缺陷，以及 通过在形成绝缘层之后形成硅化物层，形成覆盖硅化物层的相对薄的层间电介质。 构成：在硅衬底（400）上依次形成栅极绝缘层（410）和栅极多晶硅层（420）。 栅极间隔物（430）形成在栅极绝缘层和栅极多晶硅层的侧壁上。 通过使用栅极间隔物和栅极多晶硅层作为掩模，执行杂质离子注入工艺和扩散处理以在衬底中形成源极/漏极区域（440）。 形成蚀刻停止层（450）以覆盖源极/漏极区域，栅极间隔物和栅极多晶硅层。 形成覆盖蚀刻停止层的绝缘层（460）。 将绝缘层平坦化以暴露栅极多晶硅层上的蚀刻停止层。 暴露的蚀刻停止层和栅极间隔物的一部分被蚀刻以露出栅极多晶硅层的上表面和上侧表面。 硅化物层（480）选择性地形成在栅极多晶硅层的暴露部分上。

公开(公告)号：KR1020020006127A

公开(公告)日：2002-01-19

申请号：KR1020000039609

申请日：2000-07-11

Applicant: 삼성전자주식회사

Inventor： 부재필 ,  탁수영 ,  김광복 ,  김경현 ,  홍창기

IPC: H01L27/115

CPC classification number: H01L27/11526 ,  H01L27/11531

Abstract: PURPOSE: A method for manufacturing a non-volatile memory device having at least two tunnel insulation layers of different thicknesses is provided to improve a hump phenomenon of a transistor caused by a recess of an insulation layer in an isolation region, by performing a chemical mechanical polishing(CMP) process using a floating gate as a stop layer. CONSTITUTION: At least two tunnel insulation layers(32) having different thicknesses, a conductive layer(33) of a predetermined interval and the first insulation layer are sequentially formed on a semiconductor substrate(31). A predetermined depth of the resultant structure is selectively etched to form a trench, and the second insulation layer(35) is formed on the resultant structure including the trench. The second insulation layer is left only in the trench to form the isolation region. After the first insulation layer is removed, the second insulation layer is selectively eliminated by using the conductive layer as a stop layer.

Abstract translation: 目的：提供一种用于制造具有不同厚度的至少两个隧道绝缘层的非易失性存储器件的方法，以改善由隔离区域中的绝缘层的凹陷引起的晶体管的隆起现象，通过执行化学机械 抛光（CMP）工艺，使用浮动栅极作为停止层。 构成：在半导体衬底（31）上依次形成至少两层具有不同厚度的隧道绝缘层（32），预定间隔的导电层（33）和第一绝缘层。 选择性地蚀刻所得结构的预定深度以形成沟槽，并且在包括沟槽的所得结构上形成第二绝缘层（35）。 第二绝缘层仅留在沟槽中以形成隔离区。 在去除第一绝缘层之后，通过使用导电层作为停止层来选择性地去除第二绝缘层。

公开(公告)号：KR1020010011196A

公开(公告)日：2001-02-15

申请号：KR1019990030442

申请日：1999-07-26

Applicant: 삼성전자주식회사

Inventor： 윤철주 ,  홍창기 ,  윤병문

IPC: H01L21/283

Abstract: PURPOSE: A method of forming a via in a semiconductor device is to form an anchor via at an intermetal dielectric layer comprising an insulating layer of a low dielectric constant, without an overhang being generated. CONSTITUTION: A method of forming a via comprises the steps of: forming a first metal interconnect(100) formed of the first metal on a semiconductor substrate; forming a capping layer(102,104) on the metal interconnect; forming an intermetal insulating layer comprising an insulation layer(106) of a low dielectric constant on the capping layer; dry etching the intermetal insulating layer and the capping layer to form a via hole exposing the metal interconnect; forming a spacer(114) on a sidewall of the via hole; wet etching the metal interconnect exposed by the via hole to form an anchor hole(116) undercutting the capping layer; and burying a second metal into the via hole and the anchor hole to form a via plug(118).

Abstract translation: 目的：在半导体器件中形成通孔的方法是在包含低介电常数的绝缘层的金属间电介质层上形成锚通孔，而不产生突出端。 构成：形成通孔的方法包括以下步骤：在半导体衬底上形成由第一金属形成的第一金属互连（100）; 在金属互连上形成覆盖层（102,104）; 在所述覆盖层上形成包含低介电常数的绝缘层（106）的金属间绝缘层; 干蚀刻金属间绝缘层和覆盖层以形成暴露金属互连的通孔; 在所述通孔的侧壁上形成间隔物（114）; 湿式蚀刻由通孔暴露的金属互连，以形成底切盖顶盖的锚孔（116）; 并将第二金属埋入通孔和锚孔中，以形成通孔塞（118）。

公开(公告)号：KR1020000056005A

公开(公告)日：2000-09-15

申请号：KR1019990004986

申请日：1999-02-12

Applicant: 삼성전자주식회사

Inventor： 홍창기

IPC: H01L21/304

Abstract: PURPOSE: A chemical mechanical polishing apparatus is to prevent a semiconductor wafer from being polished non-uniformly due to physical and chemical variation of a polishing pad. CONSTITUTION: A chemical mechanical polishing apparatus comprises: a wafer carrier(3) which is rotatable and is able to mount a semiconductor wafer(1) such that the upper surface of the semiconductor wafer is directed to the lower direction; a polishing platen(7) including a variable part(7a) placed at a position corresponding to the lower portion of the wafer carrier and rotatable and partially movable in the up and down direction and a fixing part(7b); and a polishing pad(5) established on the polishing platen and in contact with one surface of the semiconductor wafer. The variable part of the polishing platen includes a moving unit, which allows the variable part to be movable in the up and down direction.

Abstract translation: 目的：化学机械抛光装置是为了防止半导体晶片由于抛光垫的物理和化学变化而被不均匀抛光。 构成：化学机械抛光装置包括：晶片载体（3），其可旋转并且能够安装半导体晶片（1），使得半导体晶片的上表面指向下方向; 抛光台板（7），其包括设置在与所述晶片载体的下部相对应的位置的可变部分（7a），并且可旋转并且可在上下方向上部分移动;以及固定部（7b） 以及建立在研磨台板上并与半导体晶片的一个表面接触的抛光垫（5）。 抛光台板的可变部分包括移动单元，其允许可变部分沿上下方向移动。