公开(公告)号：JPH04340644A

公开(公告)日：1992-11-27

申请号：JP21828491

申请日：1991-08-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DAGURASU GEFUAATO ,  PEGII ABAROSU

IPC: G06F1/04 ,  G06F13/36 ,  G11C11/406

Abstract: PURPOSE: To facilitate the continuous execution of a specified function by generating an affirmative response signal in response to the existence of first input when a computing device is not in an operational interruption state. CONSTITUTION: An AND gate 114 generates a CPU holding signal with output 128 and sequentially impresses it on the input 130 of a computer processor 14. When the computer processor 14 is in an operation state, a CPU holding affirmative response signal with output 132. A clock synchronization circuit 116 impresses a system holding request signal which is clock-synchronized with output 134 and impresses it on input B of a multiplexer 118. When a CPU clock is turned on and when a DISABLE signal is not impressed with the input 136 of the multiplexer 118 or with the input 126 of the AND gate 114, the CPU holding affirmative response signal generated by the computer processor 14 is generated as a system holding affirmative response signal with the output 138 of an artificial holding affirmative response device 110.

公开(公告)号：JPH04333279A

公开(公告)日：1992-11-20

申请号：JP34451391

申请日：1991-12-26

Applicant: ADVANCED MICRO DEVICES INC

Inventor： KIANOOSHIYU NASHINEE

IPC: H01L27/092 ,  H01L21/8238 ,  H03K19/003

Abstract: PURPOSE: To provide a CMOS output buffer circuit which enables substantial reduction of ground return. CONSTITUTION: This CMOS output buffer circuit for supplying output signals at an output terminal provided with a substantial reduction of the ground return is provided with a pull-up driver circuit (12), a pull-down driver circuit (14) and a control circuit (16). The pull-up driver circuit is provided with first and second resistance means for delaying the time of turning on a pull-up transistor, and the pull-down driver circuit is provided with third and forth resistance elements for delaying the time of turning for a pull-down transistor. The respective first - fourth resistance elements (D1-D4) are formed from a transmission gate and function, so as to control a gate-source voltage applied to the respective gates of the pull-up and pull-down transistors.

公开(公告)号：JPH04247751A

公开(公告)日：1992-09-03

申请号：JP24743791

申请日：1991-09-26

Applicant: ADVANCED MICRO DEVICES INC

Inventor： HAABAATO EMU CHIEN ,  ARAN EFU HENDORIKUSON

IPC: H04M1/00 ,  H04M1/253 ,  H04M1/60 ,  H04M9/08

Abstract: PURPOSE: To simplify communication between an analog device and a digital device. CONSTITUTION: This device includes a transmission attenuator 30 for operating attenuation when an outputted signal passes the transmitting circuit, and an analog/digital converting circuit 20. A receiving circuit 14 includes a reception attenautor 52 for operating attenuation when an inputted signal passes the receiving circuit, and a digital/analog converting circuit 42. The digital adjustment of the transmission attenautor and the reception attenuator can be attained by a controlling circuit 16. The control circuit senses and compares the outputted signal and the inputted signal, and decides whether the transmission or the reception is operated by this device. When the transmission is operated, the signal attenuation in the receiving circuit is increased, and the signal attenuation in the transmitting circuit is decreased. When the reception is operated, the signal attenuation in the transmitting circuit is increased, and the signal attenuation in the receiving circuit is decreased.

公开(公告)号：JPH04233353A

公开(公告)日：1992-08-21

申请号：JP12617591

申请日：1991-05-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： FUIRUTSUIN FUIRUUTSUMAN ,  GURURAJI SHIN

IPC: H04B10/20 ,  H04L12/433

Abstract: PURPOSE: To improve transmission of asynchronous data in an FDDI network. CONSTITUTION: A standard FDDI precedence algorithm is executed by programming this algorithm as a function of a token hold time(THT) in the direction of THT threshold reduction or increase for asynchronous service. If it is programmed in the direction of threshold reduction, all of data having a high priority is transmitted to a network before data having a low priority is transmitted. If it is programmed in the direction of threshold increase, data having the highest priority is first transmitted and data having a low priority level is transmitted, and this operation is repeated hereafter until the token hold time which has not been expired is made shorter than the threshold for precedence. Consequently, at least several data out of all priority-assigned data pending for transmission are transmitted to a medium at the time of acquisition of each token.

公开(公告)号：JPH04233352A

公开(公告)日：1992-08-21

申请号：JP12617491

申请日：1991-05-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： FUIRUTSUIN FUIRUUTSUMAN

IPC: H04B10/20 ,  H04L12/42 ,  H04L12/56 ,  H04L29/02

Abstract: PURPOSE: To improve the throughput of framed data in a network. CONSTITUTION: Packets of data stored in transmission and reception FIFOs in a MAC 120 are classified by tag and state bits in last words of individual packets without being mutually marked. Data to be transmitted is transferred from a system memory to the transmission FIFO, and data received from a network is stored in the reception FIFO. For the purpose of maximizing the data throughput, a determined quantity of data or a complete packet is stored in the transmission FIFO, and data is transmitted to the network while data is received from the system memory. When the determined quantity of data is stored in the reception FIFO, data is transferred to the system memory while data comes from the network.

公开(公告)号：JPH04229720A

公开(公告)日：1992-08-19

申请号：JP9932191

申请日：1991-04-30

Applicant: ADVANCED MICRO DEVICES INC

Inventor： ROBAATO DEI NOOMAN ,  SAI KIYUNGU RII ,  OMU PII AGURAWARU

IPC: H03K5/13 ,  H03K3/037 ,  H03K5/15 ,  H03K19/173 ,  H03K19/177

Abstract: PURPOSE: To provide a programmable logic device having a delay line which has a programmably selectable tap which sends an input to a programmable logic circuit. CONSTITUTION: The delay line tap gives an input to a programmable logic circuit 20 through a logic circuit drive means 18, and the means executes a preparatory processing of a quantity on the tap signal, before it is given to the programmable logic circuit. The output of the programmable logic circuit, which may be a programmable AND array 20 followed by a fixed OR array 22, is given to the edge trigger input of a dual set/reset flip flop. Other outputs of the programmable logic circuit can be selected as the input to the delay line.

公开(公告)号：JPH04227322A

公开(公告)日：1992-08-17

申请号：JP8394791

申请日：1991-04-16

Applicant: ADVANCED MICRO DEVICES INC

Inventor： KIANUUSHIYU NAHASHINEE

IPC: H03K19/018

Abstract: PURPOSE: To provide a circuit for converting a transistor/transistor logical circuit(TTL) logical level signal into a current mode logical circuit(CML) logical level signal so that immunity to a ground bounce noise, low power consumption, and high switching speed can be obtained. CONSTITUTION: A TTL-CML converting circuit includes a TTL inputting stage 20, conversion chain 22, first CML differential pair 24, level shifter 26, and second CML differential pair 28. The first CML differential pair 24 is connected between a TTL ground potential(GTTL) and a negative power supply potential(VEE). The second CML differential pair 28 is connected between a CML ground potential(GCML) and the negative power supply potential. The level shifter 26 electrically separates the TTL ground potential(GTTL) and the CML ground potential(GCML). Thus, an output signal with CML interchangeability in which a noise can be relatively absent can be generated.

公开(公告)号：JPH04225621A

公开(公告)日：1992-08-14

申请号：JP6970191

申请日：1991-04-02

Applicant: ADVANCED MICRO DEVICES INC

Inventor： OMU PURAKATSUSHIYU AGURAWARU ,  MAIKERU JIEIMUZU RAITO

IPC: G06F13/38 ,  H01L21/82 ,  H03K19/173 ,  H03K19/177

Abstract: PURPOSE: To improve flexibility in connection by supplying an output enable signal for controlling a correspondent tristate output buffer while controlling plural selectors through a configuration memory. CONSTITUTION: A programmable gate array includes plural distributed memory cells called configuration memory 200. Program data on a line 201 are loaded into a shift register 202 in response to a clock signal on a line 203. By reading a preample out of data on the line 201, a detection logic 204 determines the time when the shift register is to be full. When the shift register is full, the detection logic 204 sends a signal through a line 205 to a frame pointer logic 206 and that signal generates a frame pointer signal across a line 207.

公开(公告)号：JPH03190416A

公开(公告)日：1991-08-20

申请号：JP34117990

申请日：1990-11-30

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DONARUDO EMU UORUTAASU JIYUNIA

IPC: H03K5/151 ,  H03K5/15 ,  H03K19/00

Abstract: PURPOSE: To adjust superposed voltage by connecting respective means so that a 2nd phase clock signal is received by a 1st phase clock generation circuit means connected to a 1st delay means and a 1st phase clock signal is received by a 2nd phase clock generation circuit means. CONSTITUTION: A clock generator 8 for generating a level phase clock signal ϕ1 from a node X on an output line 10 and generating a level phase clock signal ϕ2 from a node Y on the output line 14 is formed by a 1st delay circuit 16, a 1st phase clock generation circuit 18, a 2nd delay circuit 20, and a 2nd phase clock generation circuit 22. The circuit 22 has a 1st input connected to the output of an inverter INV1 and a 2nd input connected to the output line 10 through a line 26 and the node X. An output from the circuit 22 is regulated by the node Y. Consequently adjustable superposed voltage can be obtained.

公开(公告)号：JPH03182796A

公开(公告)日：1991-08-08

申请号：JP34115990

申请日：1990-11-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DEBITSUDO EMU BAAKUSUMUUTOSUKI

IPC: H04N9/74 ,  G06T11/60 ,  G09G5/06 ,  G09G5/14

Abstract: PURPOSE: To reduce the number or faces or a memory required for a video memory by including a monitor circuit means which is provided with an input for reception of pixel position information and an output coupled to a memory means. CONSTITUTION: A monitor circuit means 23 stores information, which indicates the boundary on a screen between first and second areas, and compares pixel position information with stored area boundary information and gives the output signal to a memory means 24. It identifies a group of addressible positions including an address having color pixel information for a pixel to be displayed when the position of the pixel to be displayed is in one area. Thus, the required number of faces of a video memory 22 is reduced by using the monitor circuit 23.