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    Digital radio frequency (RF) modulator
    111.
    发明公开
    Digital radio frequency (RF) modulator 审中-公开
    数字射频调制器

    公开(公告)号：EP1898630A3

    公开(公告)日：2010-04-28

    申请号：EP07114687.2

    申请日：2007-08-21

    Applicant: STMicroelectronics Pvt. Ltd

    Inventor： Mohan Sharma, Vivek ,  Kumar Jain, Sheetal

    IPC: H04N5/00 ,  H03C1/60 ,  H03D7/16 ,  H04N5/40

    CPC classification number: H04N21/2368 ,  H04N5/40 ,  H04N21/2383

    Abstract: The present invention provides a digital radio frequency (RF) modulator for providing modulation for base-band TV signals. The RF modulator provides direct conversion of digital base-band audio and video signals to a desired RF channel frequency, without any analogue up conversion. The RF modulator in the present invention includes an audio module, a video module, and a RF converter. The audio module includes a pre-emphasis filter, a multi-stage audio interpolator and a complex frequency modulator to generate frequency modulated (FM) audio signals. The video module includes a complex VSB filter, a group-delay compensation filter and some processing logic to generate a filtered output video signal. The RF converter includes a complex adder, a complex multiplier and a RF interpolator to construct the base band TV signals and to shift the base band TV signals in a frequency domain to the desired RF channel frequency. The exponential video carrier is generated at baseband and has a frequency whose value is in the range of +/-13.5MHz. The RF interpolator includes a zero pad logic followed by a quadrature band pass filter (BPF), and an optional second stage of another zero-pad logic followed by a real band pass filter (BPF). The second stage is optional in the sense that it is required only if the desired RF channel is in the higher VHF band.

    Memory architecture for image processing
    118.
    发明公开
    Memory architecture for image processing 审中-公开
    Speicherarchitektur zur Bildverarbeitung

    公开(公告)号：EP1804214A2

    公开(公告)日：2007-07-04

    申请号：EP06027049.3

    申请日：2006-12-29

    Applicant: STMicroelectronics Pvt. Ltd.

    Inventor： Mahesh, Chandra

    IPC: G06T1/60

    CPC classification number: G06T1/60

    Abstract: The present invention relates to a memory architecture (10) for image processing comprising a memory array having multiple multi-byte memory data paths of equal multi-byte data width, and a multiplexing structure (13) connected to the output of the multiple multi-byte data paths, capable of selectively providing a multi-byte data path of a desired width containing a desired permutation of bytes chosen from one or more of the multiple data paths.

    Abstract translation: 本发明涉及一种用于图像处理的存储器架构（10），包括具有多个多字节数据宽度的多个多字节存储器数据路径的存储器阵列，以及连接到多个多字节数据宽度的输出的复用结构（13） 字节数据路径，能够选择性地提供包含从多个数据路径中的一个或多个中选择的期望的字节排列的期望宽度的多字节数据路径。

    A method of sharing testing components for multiple embedded memories and the memory system incorporating the same
    119.
    发明公开
    A method of sharing testing components for multiple embedded memories and the memory system incorporating the same 审中-公开
    一种用于几个嵌入式存储器共享的测试装置的方法和相关联的存储器系统

    公开(公告)号：EP1791133A1

    公开(公告)日：2007-05-30

    申请号：EP06124410.9

    申请日：2006-11-20

    Applicant: STMicroelectronics Pvt. Ltd.

    Inventor： Kashyap, Amit ,  Dubey, Prashant ,  Garg, Akhil

    IPC: G11C29/48 ,  G11C29/14

    CPC classification number: G11C29/48 ,  G11C29/14

    Abstract: The present invention relates to a method of sharing testing components for multiple embedded memories and the memory system incorporating the same.
    The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories.

    Abstract translation: 本发明涉及到的共享检测部件针对多个嵌入式存储器和存储器系统结合的方法。 该存储器系统包括多个测试控制器，在多个接口设备，主控制器和串行接口。 主控制器用于初始化每个使用串行接口和本地测试控制器异种存储器组的测试。 存储系统能减少布线拥塞和不同的记忆多个测试速度更快。

    A built-in self-repairable memory
    120.
    发明公开
    A built-in self-repairable memory 审中-公开
    内置自修复内存

    公开(公告)号：EP1742229A2

    公开(公告)日：2007-01-10

    申请号：EP06115639.4

    申请日：2006-06-19

    Applicant: STMicroelectronics Pvt. Ltd

    Inventor： Dubey, Prashant ,  Kashyap, Amit

    IPC: G11C29/00

    CPC classification number: G11C29/802 ,  G11C29/4401 ,  G11C29/812

    Abstract: The present invention provides a built-in self-repairable memory. The invention repairs the faulty IC through hard fuses, as well as through available redundancy in memories on chip. As the faults are not present in all the memories, the invention uses lesser number of fuses to actually make a perfect repair and thus result into a yield enhancement. The fuse data is stored in a compressed form and then decompressed at the power on. The fuse data interface with the memory to be repaired is serial. The serial links decreases the routing congestion and hence gain in area as well as gain in yield (due to lesser defects and reduced area).

    Abstract translation: 本发明提供了一种内置的可自修复存储器。 本发明通过硬熔丝以及通过片上存储器中的可用冗余来修复故障IC。 由于故障不存在于所有存储器中，因此本发明使用较少数量的保险丝来实际进行完美的修理并因此导致产量提高。 保险丝数据以压缩格式存储，然后在通电时解压缩。 与要修复的存储器的熔丝数据接口是串行的。 串行链路减少了路由拥塞，从而减少了面积以及增加收益（由于更少的缺陷和更小的面积）。

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