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公开(公告)号：EP1675266B1
公开(公告)日：2010-03-10
申请号：EP05107860.8
申请日：2005-08-26
Applicant: STMicroelectronics Pvt. Ltd
Inventor： Chatterjee, Kallol , Jain, Deependra
CPC classification number: H03K23/665 , H03K21/40 , H03K23/667
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112.发明授权A system for providing access to multiple data buffers of a data retaining and processing device 有权系统，用于对设备的访问的多个数据缓冲器，用于保持和处理数据的
公开(公告)号：EP1764703B1
公开(公告)日：2009-07-15
申请号：EP06119735.6
申请日：2006-08-29
Applicant: STMicroelectronics Pvt. Ltd.
CPC classification number: G06F13/4291 , G06F13/28 , G06F2213/0016
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公开(公告)号：EP1675266A3
公开(公告)日：2008-09-24
申请号：EP05107860.8
申请日：2005-08-26
Applicant: STMicroelectronics Pvt. Ltd
Inventor： Chatterjee, Kallol , Jain, Deependra
CPC classification number: H03K23/665 , H03K21/40 , H03K23/667
Abstract: A programmable high-speed frequency divider, in which stage for forming a frequency divider, which is capable of being programmed with a programmable dividing ratio, is simplified to reduce the area and circuit complexity. A start-up circuitry has been introduced within the said frequency-divider to ensure that the frequency-divider will never go into false state.
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公开(公告)号：EP1624704A3
公开(公告)日：2008-09-10
申请号：EP05016383.1
申请日：2005-07-28
Applicant: STMicroelectronics Pvt. Ltd
Inventor： Saha, Kaushik , Sarkar, Abhik , Maiti, Srijib Narayan
CPC classification number: H04N19/436 , H04N19/433 , H04N19/44 , H04N19/51 , H04N19/61
Abstract: A macro-block level parallel implementation of a video decoder in parallel processing environment comprising a Variable Length Decoding (VLD) block to decode the encoded Discrete Cosine Transform (DCT) coefficient; a master node which receives said decoded Discrete Cosine Transform (DCT) coefficients; and, plurality of slave nodes/processors for parallel implementation of Inverse Discrete Cosine Transform (IDCT) and motion compensation at macro-block level.
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公开(公告)号：EP1585024B1
公开(公告)日：2007-10-10
申请号：EP05102697.9
申请日：2005-04-06
Applicant: STMicroelectronics Pvt. Ltd.
Inventor： Bahl, Swapnil , Singh, Balwant
CPC classification number: G06F5/10 , G11C7/1006
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Patent Agency Ranking116.发明授权A method and device for testing of configuration memory cells in programmable logic devices (PLDS) 有权测试的方法和装置用于在可编程逻辑器件配置存储器单元（PLD）的
公开(公告)号：EP1363132B1
公开(公告)日：2007-09-05
申请号：EP03010587.8
申请日：2003-05-12
Applicant: STMicroelectronics Pvt. Ltd
Inventor： Pathak, Shalini , Swami, Parvesh
IPC: G01R31/3185 , G11C29/00 , G06F11/10
CPC classification number: G11C29/025 , G01R31/318516 , G11C29/02 , G11C29/12
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公开(公告)号：EP1804214A2
公开(公告)日：2007-07-04
申请号：EP06027049.3
申请日：2006-12-29
Applicant: STMicroelectronics Pvt. Ltd.
Inventor： Mahesh, Chandra
IPC: G06T1/60
CPC classification number: G06T1/60
Abstract: The present invention relates to a memory architecture (10) for image processing comprising a memory array having multiple multi-byte memory data paths of equal multi-byte data width, and a multiplexing structure (13) connected to the output of the multiple multi-byte data paths, capable of selectively providing a multi-byte data path of a desired width containing a desired permutation of bytes chosen from one or more of the multiple data paths.
Abstract translation: 本发明涉及一种用于图像处理的存储器架构（10），包括具有多个多字节数据宽度的多个多字节存储器数据路径的存储器阵列，以及连接到多个多字节数据宽度的输出的复用结构（13） 字节数据路径，能够选择性地提供包含从多个数据路径中的一个或多个中选择的期望的字节排列的期望宽度的多字节数据路径。
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118.发明公开A method of sharing testing components for multiple embedded memories and the memory system incorporating the same 审中-公开一种用于几个嵌入式存储器共享的测试装置的方法和相关联的存储器系统
公开(公告)号：EP1791133A1
公开(公告)日：2007-05-30
申请号：EP06124410.9
申请日：2006-11-20
Applicant: STMicroelectronics Pvt. Ltd.
Inventor： Kashyap, Amit , Dubey, Prashant , Garg, Akhil
Abstract: The present invention relates to a method of sharing testing components for multiple embedded memories and the memory system incorporating the same.
The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories.Abstract translation: 本发明涉及到的共享检测部件针对多个嵌入式存储器和存储器系统结合的方法。 该存储器系统包括多个测试控制器，在多个接口设备，主控制器和串行接口。 主控制器用于初始化每个使用串行接口和本地测试控制器异种存储器组的测试。 存储系统能减少布线拥塞和不同的记忆多个测试速度更快。
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公开(公告)号：EP1742229A2
公开(公告)日：2007-01-10
申请号：EP06115639.4
申请日：2006-06-19
Applicant: STMicroelectronics Pvt. Ltd
Inventor： Dubey, Prashant , Kashyap, Amit
IPC: G11C29/00
CPC classification number: G11C29/802 , G11C29/4401 , G11C29/812
Abstract: The present invention provides a built-in self-repairable memory. The invention repairs the faulty IC through hard fuses, as well as through available redundancy in memories on chip. As the faults are not present in all the memories, the invention uses lesser number of fuses to actually make a perfect repair and thus result into a yield enhancement. The fuse data is stored in a compressed form and then decompressed at the power on. The fuse data interface with the memory to be repaired is serial. The serial links decreases the routing congestion and hence gain in area as well as gain in yield (due to lesser defects and reduced area).
Abstract translation: 本发明提供了一种内置的可自修复存储器。 本发明通过硬熔丝以及通过片上存储器中的可用冗余来修复故障IC。 由于故障不存在于所有存储器中，因此本发明使用较少数量的保险丝来实际进行完美的修理并因此导致产量提高。 保险丝数据以压缩格式存储，然后在通电时解压缩。 与要修复的存储器的熔丝数据接口是串行的。 串行链路减少了路由拥塞，从而减少了面积以及增加收益（由于更少的缺陷和更小的面积）。
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公开(公告)号：EP1667004A3
公开(公告)日：2007-01-03
申请号：EP05111142.5
申请日：2005-11-23
Applicant: STMicroelectronics Pvt. Ltd
Inventor： Chatterjee, Kallol , Sreekiran, Samala
IPC: G05F3/24
CPC classification number: G05F3/242
Abstract: An improved first order temperature compensated reference current generator. It comprises a current device providing a controlled current, a startup circuit connected to said current device for initiating operation of said current device, and a current definition mechanism driven by said current device for supplying a current which is independent of temperature, process and individual temperature coefficients circuit elements used. The said current definition mechanism incorporates voltage controlled resistors driven by a predetermined voltage and having a predetermined temperature coefficient.
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