公开(公告)号：KR1020040043675A

公开(公告)日：2004-05-24

申请号：KR1020020072094

申请日：2002-11-19

Applicant: 삼성전자주식회사

Inventor： 선민철 ,  구자흠 ,  김철성 ,  노관종 ,  김민주

IPC: H01L21/24

CPC classification number: H01L29/6653 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78

Abstract: PURPOSE: A method for fabricating a semiconductor device by a nickel salicide process is provided to prevent silicide residue from being generated on a field region and a spacer by making a Ni-containing silicide metal layer capped with an N-rich titanium nitride layer. CONSTITUTION: A gate pattern(19) and a source/drain region(23) are formed on a silicon substrate(11). The Ni-containing silicide metal layer(25) is formed on the silicon substrate having the gate pattern and the source/drain region. The N-rich titanium nitride layer(27) is formed on the Ni-containing silicide metal layer. A heat treatment is performed on the silicon substrate including the Ni-containing silicide metal layer and the N-rich titanium nitride layer to form a nickel silicide layer on the gate pattern and the source/drain region. The Ni-containing silicide metal layer including unreacted nickel in a process for forming the nickel silicide layer and the N-rich nitride layer are selectively removed.

Abstract translation: 目的：提供一种通过镍硅化物工艺制造半导体器件的方法，以通过使含有N的氮化钛层覆盖的含Ni的硅化物金属层来防止在场区和间隔物上产生硅化物残留。 构成：在硅衬底（11）上形成栅极图案（19）和源极/漏极区域（23）。 在具有栅极图案和源极/漏极区域的硅衬底上形成含Ni的硅化物金属层（25）。 在含Ni的硅化物金属层上形成富N的氮化钛层（27）。 在包括含Ni的硅化物金属层和富N的氮化钛层的硅衬底上进行热处理，以在栅极图案和源极/漏极区上形成硅化镍层。 选择性地除去在形成硅化镍层和富N极氮化物层的工艺中包含未反应的镍的含Ni硅化物金属层。

公开(公告)号：KR1020040005330A

公开(公告)日：2004-01-16

申请号：KR1020020039834

申请日：2002-07-09

Applicant: 삼성전자주식회사

Inventor： 구자흠 ,  이창원 ,  허성준 ,  선민철 ,  윤선필

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/31612 ,  H01L27/115

Abstract: PURPOSE: A method for fabricating a semiconductor device including a silicon oxide layer is provided to reduce the generation of particles by maintaining the atmosphere of nitrogen gas within a reaction chamber before implanting silicon source gas and oxygen source gas therein. CONSTITUTION: A gate pattern is formed on an upper surface of a semiconductor substrate(S10). The semiconductor substrate is loaded into a reaction chamber in order to perform a deposition process(S20). The atmosphere of nitrogen gas is maintained within the reaction chamber by implanting nitrogen gas including nitrogen atoms into the inside of the reaction chamber(S30). A silicon oxide layer is formed on the gate pattern by supplying silicon source gas and oxygen source gas(S40). A silicon nitride layer is formed on the silicon oxide layer(S50). A double spacer is formed on a sidewall of the gate pattern(S60).

Abstract translation: 目的：提供一种用于制造包括氧化硅层的半导体器件的方法，用于在将硅源气体和氧源气体注入之前，通过将反应室内的氮气保持在反应室内来减少颗粒的产生。 构成：在半导体衬底的上表面上形成栅极图案（S10）。 将半导体衬底装载到反应室中以进行沉积处理（S20）。 通过将氮原子氮气注入到反应室的内部，将氮气保持在反应室内（S30）。 通过供给硅源气体和氧源气体，在栅极图案上形成氧化硅层（S40）。 在氧化硅层上形成氮化硅层（S50）。 在栅极图案的侧壁上形成双层间隔（S60）。

公开(公告)号：KR1020030092732A

公开(公告)日：2003-12-06

申请号：KR1020020030510

申请日：2002-05-31

Applicant: 삼성전자주식회사

Inventor： 조준규 ,  최시영 ,  윤선필 ,  김성만 ,  구자흠

IPC: H01L21/3213

CPC classification number: H01L29/518 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28247

Abstract: PURPOSE: A method for fabricating a gate pattern of a semiconductor device is provided to prevent a gate insulation layer from getting thicker in a subsequent selective oxide process even if the line width of the gate pattern reduces by performing a pretreatment process using hydrogen and nitrogen. CONSTITUTION: A gate oxide layer(110) is formed on a semiconductor substrate(100). The gate pattern(160) in which a polycrystalline silicon layer pattern(125) and a metal layer pattern(145) are sequentially stacked is formed on the gate oxide layer. A pretreatment process using process gas including hydrogen and nitrogen is performed on the semiconductor substrate including the gate pattern. A selective oxide process is performed to selectively oxidize the sidewall of the polycrystalline silicon layer pattern.

Abstract translation: 目的：提供一种用于制造半导体器件的栅极图案的方法，以便即使通过使用氢和氮进行预处理工艺来减小栅极图案的线宽，从而防止栅极绝缘层在随后的选择性氧化物工艺中变厚。 构成：在半导体衬底（100）上形成栅氧化层（110）。 在栅极氧化物层上形成依次层叠有多晶硅层图案（125）和金属层图案（145）的栅极图案（160）。 在包括栅极图案的半导体衬底上进行使用包括氢和氮的工艺气体的预处理工艺。 执行选择性氧化物处理以选择性地氧化多晶硅层图案的侧壁。

公开(公告)号：KR1020030082136A

公开(公告)日：2003-10-22

申请号：KR1020020020712

申请日：2002-04-16

Applicant: 삼성전자주식회사

Inventor： 구자흠 ,  최철준 ,  조준규 ,  허성준 ,  윤선필

IPC: H01L29/788

Abstract: PURPOSE: A flash memory device with a metal electrode is provided to improve electrical characteristics by using a metal layer such as a tungsten layer as a gate electrode, and to improve the stability of the flash memory device by controlling the reaction between the tungsten layer and a polysilicon layer. CONSTITUTION: An isolation layer is formed on a semiconductor substrate(200). A tunnel oxide layer(204) is formed on the semiconductor substrate. The first polysilicon layer pattern(206) for a floating gate is formed on the tunnel oxide layer. An interlayer dielectric(208) is formed on the first polysilicon layer pattern for the floating gate. The second polysilicon layer pattern(210) for a control gate is formed on the interlayer dielectric. A reaction barrier layer pattern is formed on the second polysilicon layer pattern for the control gate. A metal electrode layer pattern is formed on the reaction barrier layer pattern.

Abstract translation: 目的：提供具有金属电极的闪速存储器件，以通过使用诸如钨层的金属层作为栅电极来改善电特性，并且通过控制闪烁存储器件的钨层和 多晶硅层。 构成：在半导体衬底（200）上形成隔离层。 隧道氧化物层（204）形成在半导体衬底上。 用于浮置栅极的第一多晶硅层图案（206）形成在隧道氧化物层上。 在用于浮置栅极的第一多晶硅层图案上形成层间电介质（208）。 用于控制栅极的第二多晶硅层图案（210）形成在层间电介质上。 在用于控制栅极的第二多晶硅层图案上形成反应势垒层图案。 在反应阻挡层图案上形成金属电极层图案。

公开(公告)号：KR100402389B1

公开(公告)日：2003-10-17

申请号：KR1020010015150

申请日：2001-03-23

Applicant: 삼성전자주식회사

Inventor： 구자흠 ,  조만호 ,  최철준 ,  허성준

IPC: H01L21/336

CPC classification number: H01L29/4941 ,  H01L21/28088 ,  H01L21/32105 ,  H01L21/823437

Abstract: The present invention includes a method of forming a metal gate electrode on which whiskers are not formed after performing a selective oxidation process and a subsequent heating process. The metal gate electrode is formed by forming a metal gate electrode pattern which is comprised of a polysilicon layer and a metal layer, and performing a selective oxidation process. After the selective oxidation process, the metal gate electrode undergoes a subsequent heating treatment. The selective oxidation process is carried out in a nitrogen containing gas ambient, so that a metal oxide layer is minimally formed on the metal layer. As a result, it is prevented from causing whiskers on the metal layer.

Abstract translation: 本发明包括在进行选择性氧化处理和随后的加热处理之后形成其上未形成晶须的金属栅电极的方法。 金属栅电极通过形成由多晶硅层和金属层构成的金属栅电极图案并进行选择性氧化工艺而形成。 在选择性氧化处理之后，金属栅电极经历随后的加热处理。 选择性氧化过程是在含氮气体环境中进行的，从而在金属层上形成的金属氧化物层最少。 结果，防止了在金属层上引起晶须。

公开(公告)号：KR1020030029211A

公开(公告)日：2003-04-14

申请号：KR1020010061378

申请日：2001-10-05

Applicant: 삼성전자주식회사

Inventor： 허성준 ,  최시영 ,  박정우 ,  윤선필 ,  구자흠 ,  유종렬

IPC: H01L21/28

Abstract: PURPOSE: A contact line in a semiconductor device and a method for forming the same are provided to prevent a leakage current between a contact line and a semiconductor substrate, reducing resistance of the contact line. CONSTITUTION: A gate pattern(130) is formed on the active region of a semiconductor substrate(100). An ion implantation is performed using an ion implantation mask as the gate pattern. An impurity region is formed on the active region. An interlayer dielectric(160) is formed on the entire surface of the resultant structure. A contact hole(170) is formed to expose the active region. An SEG layer is formed on the exposed active region. A silicide layer(190) is formed by a silicidation process. A contact line is formed.

Abstract translation: 目的：提供半导体器件中的接触线及其形成方法，以防止接触线与半导体衬底之间的漏电流，降低接触线的电阻。 构成：在半导体衬底（100）的有源区上形成栅极图案（130）。 使用离子注入掩模作为栅极图案进行离子注入。 在有源区上形成杂质区。 在所得结构的整个表面上形成层间电介质（160）。 形成接触孔（170）以暴露活性区域。 在暴露的有源区上形成SEG层。 通过硅化工艺形成硅化物层（190）。 形成接触线。

公开(公告)号：KR1020020072654A

公开(公告)日：2002-09-18

申请号：KR1020010012600

申请日：2001-03-12

Applicant: 삼성전자주식회사

Inventor： 조만호 ,  구자흠 ,  최철준 ,  조준규 ,  허성준

IPC: H01L21/336

CPC classification number: H01L21/28061 ,  H01L21/28247

Abstract: PURPOSE: A method for forming a metal gate is provided to prevent whisker capable of causing electric short between adjacent gates after a selective oxidation process is performed for preventing abnormal oxidation of the metal gate. CONSTITUTION: A gate insulating layer and several gate material layers having a metal layer are conventionally formed on a semiconductor substrate and then etched to form a gate pattern(200). Next, the selective oxidation process is performed to selectively form a silicon oxide layer(120a) and minimize the oxidation of the metal layer. Here, due to an incomplete selective oxidation, a thin metal oxide layer(20b) is also formed on sidewalls of the metal layer. After the selective oxidation process, a heat treatment process is performed by using a gas containing hydrogen atoms to prevent whisker from occurring on the metal oxide layer(20b). The heat treatment process suppresses the surface mobility of the metal oxide layer and the nucleation of the whisker.

Abstract translation: 目的：提供一种用于形成金属栅极的方法，以防止在执行选择性氧化处理以防止金属栅极的异常氧化之后在相邻栅极之间产生电短路的晶须。 构成：通常在半导体衬底上形成具有金属层的栅极绝缘层和多个栅极材料层，然后蚀刻以形成栅极图案（200）。 接下来，进行选择氧化处理以选择性地形成氧化硅层（120a）并使金属层的氧化最小化。 这里，由于不完全的选择性氧化，金属层的侧壁上也形成有薄的金属氧化物层（20b）。 在选择氧化处理之后，通过使用含有氢原子的气体来进行热处理工艺，以防止在金属氧化物层（20b）上发生晶须。 热处理工艺抑制金属氧化物层的表面迁移率和晶须的成核。

公开(公告)号：KR100297730B1

公开(公告)日：2001-09-29

申请号：KR1019990019784

申请日：1999-05-31

Applicant: 삼성전자주식회사

Inventor： 김철성 ,  구자흠 ,  최철준 ,  김형섭

IPC: H01L29/78

Abstract: 돌출된소오스및 드레인영역을구비하는반도체장치및 그형성방법에관해개시되어있다. 본발명은반도체기판, 상기반도체기판에형성된트랜치, 상기트랜치에채워진소자분리막및 상기소자분리막위로돌출되어있는소오스및 드레인영역를구비하는반도체장치를제공한다. 따라서, 본발명을이용하면소오스및 드레인영역의접촉저항을낮추면서동시에접합누설전류도줄여그 특성을개선시킬수 있다.

公开(公告)号：KR1020000074728A

公开(公告)日：2000-12-15

申请号：KR1019990018861

申请日：1999-05-25

Applicant: 삼성전자주식회사

Inventor： 김형섭 ,  유재윤 ,  구자흠

IPC: H01L21/334

Abstract: PURPOSE: A method for manufacturing a gate structure of a semiconductor device using a liquid phase deposition is provided to form a cobalt silicide pattern, by using a silicon oxidation layer in a selective liquid phase deposition without using a selective dry etching process. CONSTITUTION: A silicon layer is formed on a semiconductor substrate(100). A photoresist layer pattern is formed on the silicon layer. The silicon layer is patterned to form a silicon pattern by using the photoresist layer pattern as an etch mask. A silicon oxidation layer(400) exposing an upper surface of the photoresist layer pattern is selectively formed in a liquid phase deposition by using a selective characteristic with the photoresist layer pattern on a semiconductor substrate exposed by the silicon pattern(250). The photoresist layer pattern is eliminated. A cobalt silicide pattern filling a gap(450) between the silicon oxidation layers is formed on the silicon pattern exposed by eliminating the photoresist layer pattern. The silicon oxidation layer is eliminated.

Abstract translation: 目的：提供使用液相沉积制造半导体器件的栅极结构的方法，以通过在选择性液相沉积中使用硅氧化层而不使用选择性干蚀刻工艺来形成钴硅化物图案。 构成：在半导体衬底（100）上形成硅层。 在硅层上形成光致抗蚀剂图案。 通过使用光致抗蚀剂层图案作为蚀刻掩模，将硅层图案化以形成硅图案。 通过使用由硅图案（250）暴露的半导体衬底上的光致抗蚀剂层图案的选择性特性，在液相沉积中选择性地形成曝光光致抗蚀剂层图案的上表面的硅氧化层（400）。 消除光致抗蚀剂层图案。 通过消除光致抗蚀剂层图案在暴露的硅图案上形成填充硅氧化层之间的间隙（450）的硅化钴图案。 消除硅氧化层。

公开(公告)号：KR100271948B1

公开(公告)日：2000-11-15

申请号：KR1019980052238

申请日：1998-12-01

Applicant: 삼성전자주식회사

Inventor： 구자흠 ,  이수근 ,  김철성 ,  서태욱 ,  이응준 ,  정주혁

IPC: H01L21/24

CPC classification number: H01L29/665 ,  H01L21/28518

Abstract: 반도체 장치의 셀프-얼라인 실리사이드 형성방법이 개시되어 있다. 반도체 기판의 상부에 게이트층을 형성하고 게이트층을 패터닝한 후, 결과물의 상부에 금속층을 형성한다. 금속층의 상부에 제1 캡핑층을 형성한 후, 기판을 제1 온도로 가열하여 게이트층의 상부에 금속 실리사이드를 형성한다. 미반응된 금속층과 제1 캡핑층을 제거한 후, 결과물의 상부에 제2 캡핑층을 형성한다. 기판을 제1 온도보다 높은 제2 온도로 가열한다. 제2 캡핑층에 의해 고온의 2차 열처리시 실리사이데이션 반응 속도를 억제하여 양호한 모폴로지를 갖는 실리사이드를 얻을 수 있다.