公开(公告)号：KR1020140008745A

公开(公告)日：2014-01-22

申请号：KR1020120075744

申请日：2012-07-11

Applicant: 삼성전자주식회사

Inventor： 김찬경 ,  차수호 ,  강동석 ,  박철우 ,  손동현 ,  이윤상 ,  김혜진

IPC: G11C11/15

CPC classification number: G11C11/165 ,  G11C5/025 ,  G11C5/04 ,  G11C7/1009 ,  G11C7/1054 ,  G11C7/1057 ,  G11C7/1081 ,  G11C7/222 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/5607 ,  G11C13/047 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008

Abstract: The present invention relates to a memory module and a memory system including a magnetic random access memory. The magnetic random access memory (MRAM) includes magnetic memory cells which are converted between the states along with a magnetization direction and an interface unit for providing various interface functions. The memory module includes a module board, one or more MRAM chips mounted on the module board, and a buffer chip for managing the operation of the MRAM chip mounted on the module board. The memory system includes a memory controller communicating with the MRAM and transmits and receives an electricity-light conversion signal or a light-electricity conversion signal using an optical connecting device connected between the MRAM and the memory controller.

Abstract translation: 本发明涉及一种存储器模块和包括磁性随机存取存储器的存储器系统。 磁性随机存取存储器（MRAM）包括磁化存储单元，其在状态与磁化方向之间转换，以及用于提供各种接口功能的接口单元。 存储器模块包括模块板，安装在模块板上的一个或多个MRAM芯片和用于管理安装在模块板上的MRAM芯片的操作的缓冲芯片。 存储器系统包括与MRAM通信的存储器控​​制器，并且使用连接在MRAM和存储器控制器之间的光学连接装置来发送和接收电光转换信号或光电转换信号。

公开(公告)号：KR1020140008665A

公开(公告)日：2014-01-22

申请号：KR1020120075459

申请日：2012-07-11

Applicant: 삼성전자주식회사

Inventor： 박철우 ,  이광섭 ,  윤철은 ,  장세영 ,  정구철 ,  한윤희

IPC: H02J7/00 ,  H01M10/44

CPC classification number: G05F1/46 ,  H04B1/1607

Abstract: An apparatus for supplying power to a portable terminal includes a battery, a power supply unit which includes at least one buck-boost converter and a plurality of regulators which are connected to the buck-boost converter, a control unit which controls the operation of the portable terminal, a touch panel which generates an input signal to the control unit, and a display unit which displays the operation of the portable terminal by the control unit. The buck-booster converter operates in a buck mode if the voltage of the battery is higher than an output voltage and operates in a boost mode if the voltage of the battery is lower than the output voltage. The regulators regulate the output voltage of the buck-boost converter to an operation voltage of each corresponding component and outputs the regulated voltage. [Reference numerals] (160) Battery; (210) Power control unit; (220) AP power supply unit; (225,235) Buck-boost converter; (230) CP power supply unit; (240) PAM power supply unit

Abstract translation: 一种用于向便携式终端供电的装置包括电池，电源单元，其包括连接到降压 - 升压转换器的至少一个降压 - 升压转换器和多个调节器，控制单元，其控制 便携式终端，产生对控制单元的输入信号的触摸面板，以及显示单元，其通过控制单元显示便携式终端的操作。 如果电池的电压高于输出电压，则降压 - 升压转换器工作在降压模式，如果电池的电压低于输出电压，则升压转换器工作在升压模式。 稳压器将降压 - 升压转换器的输出电压调节到每个相应元件的工作电压，并输出调节电压。 （附图标记）（160）电池; （210）电源控制单元; （220）AP电源单元; （225,235）降压 - 升压转换器; （230）CP电源单元; （240）PAM电源单元

公开(公告)号：KR1020140007989A

公开(公告)日：2014-01-21

申请号：KR1020120074716

申请日：2012-07-09

Applicant: 삼성전자주식회사

Inventor： 권오성 ,  박철우 ,  이윤상

IPC: G11C16/02 ,  G06F13/14 ,  G06F9/24

CPC classification number: G11C11/40615 ,  G06F9/4401 ,  G06F12/0246 ,  G11C5/04 ,  G11C16/3418 ,  G11C2211/4061

Abstract: A method for setting a user device including a nonvolatile random access memory includes the steps of: reading a bias set inputted by the user; and setting a refresh period for the nonvolatile random access memory in a mode register according to the bias set. The refresh mode includes a refresh inactivation mode for the nonvolatile random access memory and refresh execution modes corresponding to a plurality of different periods.

Abstract translation: 一种用于设置包括非易失性随机存取存储器的用户设备的方法，包括以下步骤：读取由用户输入的偏差集合; 以及根据偏置集在模式寄存器中设置非易失性随机存取存储器的刷新周期。 刷新模式包括用于非易失性随机存取存储器的刷新失活模式和对应于多个不同周期的刷新执行模式。

公开(公告)号：KR1020130119545A

公开(公告)日：2013-11-01

申请号：KR1020120042413

申请日：2012-04-24

Applicant: 삼성전자주식회사

Inventor： 서은성 ,  박철우 ,  황홍선

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C7/00 ,  G11C11/40611

Abstract: A memory system includes at least one memory device and a memory controller. The memory device includes a refresh request circuit which generates a refresh data signal which includes a refresh request signal according to each data retention time of a plurality of memory cells. The memory controller controls the memory device by scheduling an operation command about the operation of the memory device by including the refresh request signal.

Abstract translation: 存储器系统包括至少一个存储器设备和存储器控制器。 存储装置包括根据多个存储单元的每个数据保留时间产生包括刷新请求信号的刷新数据信号的刷新请求电路。 存储器控制器通过包括刷新请求信号调度关于存储器件的操作的操作命令来控制存储器件。

公开(公告)号：KR1020130085612A

公开(公告)日：2013-07-30

申请号：KR1020120006488

申请日：2012-01-20

Applicant: 삼성전자주식회사

Inventor： 강상범 ,  김찬경 ,  박철우 ,  오형록

IPC: G11C13/00 ,  G11C16/34 ,  G11C16/12

CPC classification number: G11C13/0069 ,  G11C13/0038 ,  G11C13/004 ,  G11C2207/2254

Abstract: PURPOSE: A resistivity memory device and a calibration method thereof are provided to control the source line voltage and the program voltage, thereby improving the program reliability of the resistivity memory device. CONSTITUTION: The calibration voltage is applied to a source line of a plurality of memory cell, and the plurality of memory cell is programmed in a target status. Depending on the program result, the calibration voltage is determined as the source line voltage (S150). The program voltage which programs the plurality of memory cell is determined (S190). The program of the plurality of memory cell is performed by the difference of the source line voltage and the program voltage. The program voltage is applied to a bit line of the plurality of memory cell.

Abstract translation: 目的：提供电阻率存储器件及其校准方法来控制源极线电压和编程电压，从而提高电阻率存储器件的程序可靠性。 构成：将校准电压施加到多个存储单元的源极线，并且将多个存储单元编程为目标状态。 根据程序结果，校准电压被确定为源极线电压（S150）。 确定编程多个存储单元的编程电压（S190）。 多个存储单元的程序由源极线电压和编程电压的差来执行。 将编程电压施加到多个存储单元的位线。

公开(公告)号：KR1020130042779A

公开(公告)日：2013-04-29

申请号：KR1020110106857

申请日：2011-10-19

Applicant: 삼성전자주식회사

Inventor： 김수아 ,  김진호 ,  박철우

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/10876 ,  H01L27/10885 ,  H01L27/228 ,  H01L27/2454 ,  H01L29/66712

Abstract: PURPOSE: A semiconductor device including a vertical channel transistor and a method for fabricating the same are provided to prevent floating by connecting channel regions using a string body connection part. CONSTITUTION: A first insulating layer(DL1) is arranged on a substrate. A buried bitline(BBL) is arranged on the first insulating layer. Active pillars(AP) include a channel region. A contact gate electrode is extended adjacently to the channel region. A string body connection part connects the channel regions.

Abstract translation: 目的：提供一种包括垂直沟道晶体管的半导体器件及其制造方法，以通过使用串体连接部分连接沟道区域来防止浮动。 构成：在衬底上布置第一绝缘层（DL1）。 掩埋位线（BBL）布置在第一绝缘层上。 活动支柱（AP）包括通道区域。 接触栅电极相邻于沟道区延伸。 弦体连接部分连接通道区域。

公开(公告)号：KR1020130022540A

公开(公告)日：2013-03-07

申请号：KR1020110085146

申请日：2011-08-25

Applicant: 삼성전자주식회사

Inventor： 김찬경 ,  황홍선 ,  박철우 ,  강상범 ,  오형록

IPC: G11C16/26 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C11/1673 ,  G11C11/1697 ,  G11C11/2273 ,  G11C11/2297 ,  G11C13/0038 ,  G11C13/004 ,  G11C16/30

Abstract: PURPOSE: A data read circuit, a nonvolatile memory device including the same, and a method for reading data in the nonvolatile memory device are provided to improve the reliability of read data by using a plurality of reference voltages. CONSTITUTION: A cell array includes nonvolatile memory cells. A bit line is connected to the nonvolatile memory cell and transmits a data voltage(VSA). A sense amplifier circuit(1151) receives a data voltage through a first input unit and receives two reference voltages(VREFH,VREFL) through a second input unit. The sense amplifier circuit generates read data by differentially amplifying input signals inputted to the first and second input units in a data read operation.

Abstract translation: 目的：提供数据读取电路，包括该数据读取电路的非易失性存储器件以及用于读取非易失性存储器件中的数据的方法，以通过使用多个参考电压来提高读取数据的可靠性。 构成：单元阵列包括非易失性存储单元。 位线连接到非易失性存储单元并发送数据电压（VSA）。 读出放大器电路（1151）通过第一输入单元接收数据电压，并通过第二输入单元接收两个参考电压（VREFH，VREFL）。 读出放大器电路通过在数据读取操作中差分放大输入到第一和第二输入单元的输入信号来产生读取数据。

公开(公告)号：KR1020130020333A

公开(公告)日：2013-02-27

申请号：KR1020110082910

申请日：2011-08-19

Applicant: 삼성전자주식회사

Inventor： 유학수 ,  박철우 ,  정현우 ,  황홍선 ,  김수아 ,  최현호

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/336

CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/66712

Abstract: PURPOSE: A semiconductor device including a vertical channel transistor and a manufacturing method thereof are provided to prevent a channel region from being floated by connecting channel regions of active pillars to a string body connection unit. CONSTITUTION: A plurality of active pillars(AP) include a top dopant region, a bottom dopant region, and a channel region(C). The channel region is arranged between the top dopant region and the bottom dopant region. A contact gate electrode(CG) is contacted with a word line extended in a first direction and is extended near the channel region. A bit line is extended in a second direction across the first direction and is contacted with the bottom dopant region. A string body connection unit(SB) connects the channel regions of adjacent active pillars.

Abstract translation: 目的：提供一种包括垂直沟道晶体管及其制造方法的半导体器件，以通过将活性柱的沟道区域连接到串体连接单元来防止沟道区域浮起。 构成：多个活性柱（AP）包括顶部掺杂区域，底部掺杂剂区域和沟道区域（C）。 沟道区布置在顶部掺杂区域和底部掺杂区域之间。 接触栅电极（CG）与在第一方向上延伸的字线接触并在沟道区附近延伸。 位线沿着第一方向在第二方向上延伸并与底部掺杂剂区域接触。 弦体连接单元（SB）连接相邻活动柱的通道区域。

公开(公告)号：KR1020130018487A

公开(公告)日：2013-02-25

申请号：KR1020120037553

申请日：2012-04-10

Applicant: 삼성전자주식회사

Inventor： 강욱성 ,  박철우 ,  유학수 ,  황홍선

IPC: G11C7/22 ,  G11C8/18 ,  G11C7/12 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C8/14 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096

Abstract: PURPOSE: A memory device for managing hidden timing parameters is provided to secure timing parameter margin by hiding the timing parameters from a memory controller. CONSTITUTION: A memory device includes a plurality of banks in which a plurality of memory cells are arranged. Each bank includes two or more sub banks. In a sub bank interleave method to continuously operate the sub banks in one bank one by one, a continuous operation between sub banks is set at low active-to-low active time interval between different banks.

Abstract translation: 目的：提供一种用于管理隐藏定时参数的存储器件，以通过从存储器控制器隐藏定时参数来保护定时参数余量。 构成：存储器件包括多个存储单元，多个存储单元布置在该存储单元中。 每个银行都有两个或更多的子银行。 在子库交织方法中，一个接一个地连续操作一个子组中的子组，子组之间的连续操作被设置为不同组之间的低有效 - 低活动时间间隔。

公开(公告)号：KR101146531B1

公开(公告)日：2012-05-25

申请号：KR1020050034608

申请日：2005-04-26

Applicant: 삼성전자주식회사

Inventor： 홍성진 ,  박철우 ,  민웅규

IPC: G09G3/36 ,  G02F1/133 ,  G09G3/20

CPC classification number: G09G3/3648 ,  G09G2300/0491 ,  G09G2310/0251 ,  G09G2310/061 ,  G09G2320/0261 ,  G09G2360/18

Abstract: 효율적인 임펄시브 구동방식을 갖는 액정표시장치와, 이의 구동 장치 및 구동 방법이 개시된다. 표시패널은 영상을 표시한다. 타이밍 제어부는 입력되는 제어신호를 근거로 제1 제어신호 및 제2 제어신호를 출력한다. 데이터 구동부는 제1 제어신호에 기초하여 제1 구간 동안 비정상데이터신호를 표시패널에 출력하고, 제2 구간 동안 정상데이터신호를 표시패널에 각각 출력한다. 게이트 구동부는 제2 제어신호에 기초하여 제1 구간의 일부구간까지 확장된 제1 게이트 펄스와 제2 구간에 대응하는 제2 게이트 펄스를 갖는 게이트 신호를 표시패널에 출력한다. 이에 따라, 임펄시브 구동시 정상 데이터전압의 충전율을 향상시킴으로써 동영상의 표시 품질을 더욱 향상시킬 수 있다.
임펄시브 구동, 충전율, 동영상, OCB