公开(公告)号：KR1020110101983A

公开(公告)日：2011-09-16

申请号：KR1020100021391

申请日：2010-03-10

Applicant: 삼성전자주식회사

Inventor： 김창정 ,  김영배 ,  허지현 ,  이동수 ,  장만 ,  이창범 ,  이승렬

IPC: H01L21/8222

CPC classification number: H01L45/085 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1675

Abstract: 바이폴라 메모리셀 및 이를 포함하는 메모리소자에 관해 개시되어 있다. 개시된 바이폴라 메모리셀은 프로그래밍 방향이 서로 반대인 두 개의 바이폴라 메모리층을 포함할 수 있다. 상기 두 개의 바이폴라 메모리층은 중간전극을 사이에 두고 연결될 수 있다. 상기 두 개의 바이폴라 메모리층은 동일 구조 또는 반대 구조를 가질 수 있다.

公开(公告)号：KR1020110074361A

公开(公告)日：2011-06-30

申请号：KR1020090131298

申请日：2009-12-24

Applicant: 삼성전자주식회사 ,  성균관대학교산학협력단

Inventor： 박재철 ,  권기원 ,  허지현 ,  송이헌 ,  김창정

IPC: G09G3/36 ,  G09G3/20

Abstract: PURPOSE: A gate driving device and a gate driving method are provided to recycle a next pixel row by providing current discharged from a previous pixel row for the next pixel column. CONSTITUTION: A plurality of shifts(101,102,103,104) include a set signal input terminal, a first clock input terminal, a second clock input terminal, and an output terminal. A plurality of switches transfer the residual current discharged from each shift to the output of the other shift. A switch control unit(120) controls switching operations of a plurality of switches. A clock generator(110) generates a plurality of clocks to be inputted into the first clock input terminal and the second clock input terminal. The clock generator repeatedly generates sequentially three phase-shifted clock signals.

Abstract translation: 目的：提供一种栅极驱动装置和栅极驱动方法，用于通过从下一像素列的先前像素行排出的电流来再循环下一个像素行。 构成：多个位移（101,102,103,104）包括设定信号输入端子，第一时钟输入端子，第二时钟输入端子和输出端子。 多个开关将从每个移位放电的剩余电流传送到另一个移位的输出。 开关控制单元（120）控制多个开关的开关动作。 时钟发生器（110）产生要输入到第一时钟输入端和第二时钟输入端的多个时钟。 时钟发生器反复产生三个相移时钟信号。

公开(公告)号：KR1020110074355A

公开(公告)日：2011-06-30

申请号：KR1020090131292

申请日：2009-12-24

Applicant: 삼성전자주식회사

Inventor： 전상훈 ,  송이헌 ,  김창정 ,  박성호

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78618 ,  H01L29/45

Abstract: PURPOSE: A transistor is provided to prevent etching issue, lack of uniformity, and a leakage current by increasing threshold voltage through an insertion layer between a source electrode and a channel layer. CONSTITUTION: In a transistor, a channel layer(C1) including an oxide semiconductor is formed on a substrate(SUB1). A gate electrode(G1) is formed on the channel layer. A source electrode(S1) and a drain electrode(D1) are respectively contacted with both ends of the channel layer. A semiconductor insertion layer(A1) is formed between the source electrode and the channel layer. A potential barrier between the source electrode and the channel layer is increased by the semiconductor insertion layer.

Abstract translation: 目的：提供晶体管，以通过增加源电极和沟道层之间的插入层的阈值电压来防止蚀刻问题，缺乏均匀性和漏电流。 构成：在晶体管中，在衬底（SUB1）上形成包括氧化物半导体的沟道层（C1）。 在沟道层上形成栅电极（G1）。 源电极（S1）和漏电极（D1）分别与沟道层的两端接触。 在源电极和沟道层之间形成半导体插入层（A1）。 源电极和沟道层之间的势垒由半导体插入层增加。

公开(公告)号：KR1020100130419A

公开(公告)日：2010-12-13

申请号：KR1020090049093

申请日：2009-06-03

Applicant: 삼성전자주식회사

Inventor： 김기환 ,  김영배 ,  이승렬 ,  박영수 ,  김창정 ,  강보수

IPC: H01L29/861

CPC classification number: H01L27/1021 ,  H01L27/24 ,  H01L29/16 ,  H01L29/22 ,  H01L29/26 ,  H01L29/267 ,  H01L29/861

Abstract: PURPOSE: A hetero-junction diode, a method of manufacturing the same and an electronic device comprising hetero-junction diode are provided to help a user to manufacture a diode under low temperature without high price precious metal by forming one of a bottom electrode and an top electrode with a non-precious material. CONSTITUTION: A p-type non-oxidizing layer(20) is formed on a bottom electrode(10). A n-type oxide layer(30) is formed on the p-type non-oxidizing layer. A top electrode(40) is formed on the n-type oxide layer. One of the top electrode and the bottom electrode is manufactured by the non precious metal. The work function of the non-oxidizing layer is higher than that of the oxide layer by 0.8~1.2 eV.

Abstract translation: 目的：提供异相结二极管及其制造方法以及包括异质结二极管的电子器件，以帮助用户在低温下制造二极管，而不需要高价格的贵金属，通过形成底电极和 顶部电极与非贵重材料。 构成：在底部电极（10）上形成p型非氧化层（20）。 在p型非氧化层上形成n型氧化物层（30）。 顶部电极（40）形成在n型氧化物层上。 顶部电极和底部电极之一由非贵金属制成。 非氧化层的功函数比氧化层的功函数高0.8〜1.2eV。

公开(公告)号：KR1020100098137A

公开(公告)日：2010-09-06

申请号：KR1020090017158

申请日：2009-02-27

Applicant: 삼성전자주식회사

Inventor： 박성호 ,  허지현 ,  김창정 ,  김상욱 ,  송이헌

IPC: H01L21/8238

Abstract: PURPOSE: An inverter and a logic device comprising the same is provided to improve the operation property of an inverter by increasing the sub-threshold slope of a load transistor through a second insertion layer. CONSTITUTION: A pass transistor (T1) and a load transistor(T2) are successively laminated in a substrate(SUB1). The first insulating layer(IL1) is formed on the substrate. A first gate(G1) is formed on the first insulating layer. A channel layer(C1') consisting of a crystalline semiconductor which is formed between the first gate insulating layer(GI1) and a first channel layer(C1). A first source electrode and a first drain electrode are formed on the first gate insulating layer. A first body gate isolation layer(BGI1) is formed on the first source electrode and the first drain electrode.

Abstract translation: 目的：提供一种逆变器及包括该逆变器及其逻辑装置，以通过第二插入层增加负载晶体管的次阈值斜率来提高逆变器的操作性能。 构成：在衬底（SUB1）中依次层叠通过晶体管（T1）和负载晶体管（T2）。 在基板上形成第一绝缘层（IL1）。 在第一绝缘层上形成第一栅极（G1）。 由在第一栅极绝缘层（GI1）和第一沟道层（C1）之间形成的晶体半导体构成的沟道层（C1'）。 在第一栅极绝缘层上形成第一源电极和第一漏电极。 第一体栅极隔离层（BGI1）形成在第一源电极和第一漏电极上。

公开(公告)号：KR1020100082576A

公开(公告)日：2010-07-19

申请号：KR1020090001942

申请日：2009-01-09

Applicant: 삼성전자주식회사

Inventor： 김상욱 ,  박성호 ,  김창정 ,  김선일

IPC: H01L29/786 ,  C09K13/04

CPC classification number: H01L29/7869 ,  H01L29/26

Abstract: PURPOSE: An oxide semiconductor and a thin film transistor including the same are provided to improve the stability and the reliability of the oxide semiconductor by adding hafnium to an indium oxide. CONSTITUTION: An oxide layer(12) is formed on a substrate(11) by a thermal oxidation process. A gate electrode(13) is formed on the oxide layer. A gate insulating layer(14) is formed on the substrate and the gate electrode. A channel(15) is formed on the gate insulating layer by adding hafnium to an indium oxide. A source(16a) and a drain(16b) are formed on both sides of the channel and the insulating layer.

Abstract translation: 目的：提供一种氧化物半导体和包括该氧化物半导体的薄膜晶体管，以通过向氧化铟中加入铪来提高氧化物半导体的稳定性和可靠性。 构成：通过热氧化工艺在衬底（11）上形成氧化物层（12）。 在氧化物层上形成栅电极（13）。 栅极绝缘层（14）形成在衬底和栅电极上。 通过向氧化铟添加铪，在栅极绝缘层上形成沟道（15）。 源极（16a）和漏极（16b）形成在沟道和绝缘层的两侧。

公开(公告)号：KR1020100081836A

公开(公告)日：2010-07-15

申请号：KR1020090001250

申请日：2009-01-07

Applicant: 삼성전자주식회사

Inventor： 박성호 ,  송이헌 ,  김창정 ,  김상욱 ,  김선일

IPC: H01L27/04 ,  H01L29/786 ,  H01L29/78

CPC classification number: H01L29/7869 ,  H01L29/4232 ,  H01L29/7424 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/78696

Abstract: PURPOSE: A logical circuit device including stacked semiconductor oxide transistors is provided to convert transistors from a depletion mode to an enhancement mode by regulating a threshold voltage between transistors. CONSTITUTION: A first semiconductor oxide transistor includes a first semiconductor oxide channel layer(CH1). A second semiconductor transistor includes a second semiconductor oxide channel layer(CH2). A body gate(V_body) is located between the first transistor and the second transistor. A negative voltage is applied to the body gate, and the threshold voltages of the first transistor and the second transistor are transferred toward a positive direction. A first gate oxide(GOX1) is formed between the body gate and the first channel layer. A second gate oxide(GOX2) is formed between the body gate and the second channel layer.

Abstract translation: 目的：提供包括堆叠的半导体氧化物晶体管的逻辑电路器件，以通过调节晶体管之间的阈值电压将晶体管从耗尽模式转换为增强模式。 构成：第一半导体氧化物晶体管包括第一半导体氧化物沟道层（CH1）。 第二半导体晶体管包括第二半导体氧化物沟道层（CH2）。 体栅（V_body）位于第一晶体管和第二晶体管之间。 向体栅施加负电压，第一晶体管和第二晶体管的阈值电压向正方向转移。 第一栅极氧化物（GOX1）形成在体栅和第一沟道层之间。 第二栅极氧化物（GOX2）形成在体栅和第二沟道层之间。

公开(公告)号：KR1020100062570A

公开(公告)日：2010-06-10

申请号：KR1020080121277

申请日：2008-12-02

Applicant: 삼성전자주식회사

Inventor： 이창범 ,  김창정 ,  이동수

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  G11C13/0004

Abstract: PURPOSE: A resistivity random access memory device is provided to steadily be driven in a high temperature by doping a material with the high oxygen affinity on a memory resistant layer in which information is stored. CONSTITUTION: A memory resistor(11) is located between a first electrode(10) and a second electrode(12). The first electrode and the second electrode are formed with a conductive material. The memory resistor is a transition metal oxide in which metal with the high oxygen affinity is dopped. The metal has the oxygen affinity which is higher than that of the transition metal of the transition metal oxide. A switch structure is formed on the first electrode. A middle electrode is formed between the switch structure and the memory resistor.

Abstract translation: 目的：提供一种电阻率随机存取存储器件，通过在存储信息的存储器层上掺杂高氧亲和力的材料，稳定地在高温下被驱动。 构成：存储电阻（11）位于第一电极（10）和第二电极（12）之间。 第一电极和第二电极由导电材料形成。 记忆电阻是其中掺杂有高氧亲和力的金属的过渡金属氧化物。 金属的氧亲和力高于过渡金属氧化物的过渡金属。 在第一电极上形成开关结构。 在开关结构和存储电阻之间形成中间电极。

公开(公告)号：KR1020090131171A

公开(公告)日：2009-12-28

申请号：KR1020080057018

申请日：2008-06-17

Applicant: 삼성전자주식회사

Inventor： 김상욱 ,  박영수 ,  김창정

IPC: G06F3/047 ,  G06F3/041 ,  B82Y30/00

CPC classification number: G06F3/0414 ,  G06F2203/04103 ,  H01B5/14

Abstract: PURPOSE: A touch panel using a nano wire is provided to employ a ZnO nano wire with a piezoelectric constant and a high penetration ratio as a piezoelectric device, thereby improving performance of the touch panel. CONSTITUTION: A first transparent electrode layer(12) is arranged on a first transparent substrate(11). A plurality of piezoelectricity nano wires(13) are perpendicularly arranged on the first transparent electrode layer. An optical permeability nano wire layer is formed by the piezoelectricity nano wires. A second transparent electrode layer(16) is arranged on the nano wire layer. A second transparent substrate(17) is arranged on the second transparent electrode layer. ZnO nano wires are able to be used as the piezoelectricity nano wires.

Abstract translation: 目的：提供使用纳米线的触摸面板，以使用压电常数和高穿透率的ZnO纳米线作为压电元件，从而提高触摸面板的性能。 构成：第一透明电极层（12）布置在第一透明基板（11）上。 多个压电纳米线（13）垂直布置在第一透明电极层上。 通过压电纳米线形成透光性纳米线层。 第二透明电极层（16）布置在纳米线层上。 第二透明基板（17）布置在第二透明电极层上。 ZnO纳米线能够用作压电纳米线。

公开(公告)号：KR1020090124329A

公开(公告)日：2009-12-03

申请号：KR1020080050466

申请日：2008-05-29

Applicant: 삼성전자주식회사

Inventor： 김창정 ,  김상욱 ,  김선일

IPC: H01L29/786 ,  H01L21/20

CPC classification number: H01L29/78693 ,  H01L29/26

Abstract: PURPOSE: An oxide semiconductor and thin film transistor comprising the same are provided to improve the electrical characteristic and the mobility by using the ZnO based material layer in the channel region of the thin film transistor. CONSTITUTION: The oxide semiconductor includes Zn, In and Hf. The oxide semiconductor has the composition ratio of Hf in range of 3~16at%. The channel(15) comprises Zn, and In and Hf corresponding to the gate(13). The gate insulator is formed between the gate and channel. The gate isolation layer(14) is formed in the substrate(11) and the upper part of the gate. The source(16a) and drain(16b) are formed in the upper part of gate isolation layer and both side part of channel.

Abstract translation: 目的：提供包含该氧化物半导体和薄膜晶体管的氧化物半导体和薄膜晶体管，以通过在薄膜晶体管的沟道区域中使用ZnO基材料层来改善电特性和迁移率。 构成：氧化物半导体包括Zn，In和Hf。 氧化物半导体的组成比Hf为3〜16at％。 通道（15）包括Zn，In和Hf对应于栅极（13）。 栅极绝缘体形成在栅极和沟道之间。 栅极隔离层（14）形成在基板（11）和栅极的上部。 源极（16a）和漏极（16b）形成在栅极隔离层的上部和沟道的两侧。