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公开(公告)号：KR1020040070564A
公开(公告)日：2004-08-11
申请号：KR1020030006728
申请日：2003-02-04
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: PURPOSE: A ferroelectric capacitor and a fabricating method thereof are provided to maintain stably a state of polarization during a long retention period by laminating dielectric layers in case of different composition or laminating heterogeneous dielectric layers having different composition ratios in case of the same composition. CONSTITUTION: A ferroelectric capacitor includes a lamination structure of a bottom electrode(40), a dielectric layer(42), and a top electrode(44). The dielectric layer is formed by laminating sequentially a plurality of double-layered ferroelectric layers. Two adjacent double-layered ferroelectric layers of the double-layered ferroelectric layers are heterogeneous in a composition or in a composition ratio. An intermediate layer is formed between the bottom electrode and the dielectric layer or between the top electrode and the dielectric layer.
Abstract translation: 目的：提供强电介质电容器及其制造方法，以在组合不同的情况下，通过层叠电介质层，在相同组成的情况下层压具有不同组成比的非均相介电层，可以在长时间保持期间保持极化状态。 构成：铁电电容器包括底部电极（40），电介质层（42）和顶部电极（44）的叠层结构。 介电层通过依次层叠多层双层铁电体层而形成。 双层铁电体层的两个相邻的双层铁电体层的组成或组成比是非均质的。 在底部电极和电介质层之间或在顶部电极和电介质层之间形成中间层。
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公开(公告)号：KR1020100002205A
公开(公告)日：2010-01-06
申请号：KR1020090057210
申请日：2009-06-25
Applicant: 삼성전자주식회사
IPC: H01L21/8242 , H01L27/108
CPC classification number: H01L27/2481 , H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
Abstract: PURPOSE: A memory device and a manufacturing method of the same are provided to prevent the deterioration of a memory device and a switch structure by forming an insulating layer since a source does not include hydrogen. CONSTITUTION: In a memory device and a manufacturing method of the same, a first electrode(11) is formed. Memory nodes(12, 14) are formed on the first electrode. An insulating layer is contacted to the memory node and is formed with a source material without hydrogen. The second electrode(13) is formed on the memory node. The memory node is formed with a transition metal oxide having the resistance change property.
Abstract translation: 目的：提供一种存储器件及其制造方法，用于通过形成绝缘层来防止存储器件和开关结构的劣化，因为源不包括氢。 构成：在存储器件及其制造方法中，形成第一电极（11）。 存储器节点（12,14）形成在第一电极上。 绝缘层与存储器节点接触并且形成有不含氢的源材料。 第二电极（13）形成在存储器节点上。 记忆节点形成有具有电阻变化特性的过渡金属氧化物。
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公开(公告)号：KR1020090029558A
公开(公告)日：2009-03-23
申请号：KR1020070094898
申请日：2007-09-18
Applicant: 삼성전자주식회사
IPC: H01L29/861
CPC classification number: H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2481 , H01L29/24 , H01L29/242 , H01L29/267 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/146
Abstract: A diode and a memory device comprising the same are provided to implement the high integration of memory device by increasing the forward current density of N-type and P-type semiconductor layers. A diode(100) comprises the resistance alteration material. The resistance alteration material comprises either P-type or N-type semiconductor layer(10,20). The resistance of the resistance alteration material is changed according to the applied voltage. The memory device comprises the diode and the storage node. The diode has the resistance alteration material in either P-type or N-type semiconductor layer.
Abstract translation: 提供二极管和包括该二极管的存储器件以通过增加N型和P型半导体层的正向电流密度来实现存储器件的高集成度。 二极管（100）包括电阻改变材料。 电阻改变材料包括P型或N型半导体层（10,20）。 电阻变化材料的电阻根据施加的电压而改变。 存储器件包括二极管和存储节点。 二极管具有P型或N型半导体层中的电阻改变材料。
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公开(公告)号：KR1020090018504A
公开(公告)日：2009-02-20
申请号：KR1020070082989
申请日：2007-08-17
Applicant: 삼성전자주식회사
IPC: H01L29/86 , H01L29/861
CPC classification number: H01L29/242 , H01L27/1021 , H01L27/24 , H01L29/24 , H01L29/267 , H01L29/8618
Abstract: A diode structure and a memory device including the same are provided to obtain a high rectifying characteristic by increasing a forward/backward current ratio and a forward current density. A diode structure includes a first electrode(11), a p-type Cu oxide layer(12), an n-type InZn oxide layer(13) and a second electrode(14). The p-type Cu oxide layer is formed on the first electrode. The n-type InZn oxide layer is formed on the p-type Cu oxide layer. The second electrode is formed on the n-type InZn oxide. The p-type Cu oxide layer includes CuO. The n-type InZn oxide layer includes InZnO. The first electrode and the second electrode are made of metal or conductive metal oxide. The diode structure is formed by a PVD(Physical Vapor Deposition), an ALD(Atomic Layer Deposition) or a CVD(Chemical Vapor Deposition) method.
Abstract translation: 提供二极管结构和包括该二极管结构的存储器件以通过增加正向/反向电流比和正向电流密度来获得高整流特性。 二极管结构包括第一电极（11），p型Cu氧化物层（12），n型InZn氧化物层（13）和第二电极（14）。 p型Cu氧化物层形成在第一电极上。 n型InZn氧化物层形成在p型Cu氧化物层上。 第二电极形成在n型InZn氧化物上。 p型Cu氧化物层包括CuO。 n型InZn氧化物层包括InZnO。 第一电极和第二电极由金属或导电金属氧化物制成。 二极管结构由PVD（物理气相沉积），ALD（原子层沉积）或CVD（化学气相沉积）法形成。
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公开(公告)号：KR1020100078808A
公开(公告)日：2010-07-08
申请号：KR1020080137169
申请日：2008-12-30
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/04 , G11C13/0004 , H01L27/2409 , H01L45/1233 , H01L45/146
Abstract: PURPOSE: A resistivity memory device is provided to improve the reliability of the device by preventing the deterioration of a switching device and an error in reducing information. CONSTITUTION: At least more than one first electrode(E1) is formed on a substrate(SUB1). At least one second electrode(E2) is separated from the first electrode. A first lamination structure(S1) is interposed between the first and the second electrode. The first lamination structure comprises a first interlayer electrode(M1) having a barrier layer(b1). The barrier layer comprises at least one of a conductive metal nitride and a conductive metal oxide.
Abstract translation: 目的：提供电阻率记忆装置，通过防止开关装置的劣化和减少信息的误差来提高装置的可靠性。 构成：在衬底（SUB1）上形成至少多于一个第一电极（E1）。 至少一个第二电极（E2）与第一电极分离。 第一层压结构（S1）插在第一和第二电极之间。 第一层压结构包括具有阻挡层（b1）的第一层间电极（M1）。 阻挡层包括导电金属氮化物和导电金属氧化物中的至少一种。
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Patent Agency Ranking
公开(公告)号：KR1020090103113A
公开(公告)日：2009-10-01
申请号：KR1020080028496
申请日：2008-03-27
Applicant: 삼성전자주식회사
IPC: H01L27/04
CPC classification number: H01L23/49833 , G11C5/02 , G11C5/04 , G11C5/063 , H01L23/481 , H01L25/18 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A semiconductor device and manufacturing method is provided to increase the degree of integration of the memory device. CONSTITUTION: The semiconductor device includes the memory array(100), and the peripheral circuit(200). The memory array is formed in the first substrate(S1). The peripheral circuit is formed in the second substrate(S2). The first and the second substrate are mutually attached to the memory array and peripheral circuit to be electrically connected. One of the first and the second substrate is the glass substrates, the intensification(hard) plastic substrate, the flexible plastic substrate, the Si substrate, and the GaAs substrate and SiN substrate.
Abstract translation: 目的：提供半导体器件和制造方法以增加存储器件的集成度。 构成：半导体器件包括存储器阵列（100）和外围电路（200）。 存储器阵列形成在第一衬底（S1）中。 外围电路形成在第二基板（S2）中。 第一和第二基板相互连接到存储器阵列和外围电路以电连接。 第一和第二基板之一是玻璃基板，强化（硬）塑料基板，柔性塑料基板，Si基板以及GaAs基板和SiN基板。
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公开(公告)号：KR1020090081153A
公开(公告)日：2009-07-28
申请号：KR1020080007082
申请日：2008-01-23
Applicant: 삼성전자주식회사
IPC: H01L27/108
CPC classification number: H01L27/24 , G11C13/00 , G11C13/0007 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
Abstract: A resistivity memory device and a manufacturing method thereof by using the resistance of the resistance alteration material are provided to maintain the resistance law of the first resistance alteration layer although the lateral part of the first resistance alteration layer is damaged by etching. A resistivity memory device comprises a first electrode(100), a first insulation layer, a first resistance alteration layer(120) and a first switching device. The first insulation layer is equipped on the first electrode. The first insulation layer has the first hole exposing a part of the first electrode. The first resistance alteration layer is contacted with the exposed first electrode. The first resistance alteration layer is expanded on the first insulation layer of the first around hole. The first switching device is electrically connected to the first resistance alteration layer.
Abstract translation: 提供了使用电阻变化材料的电阻的电阻率存储装置及其制造方法，以保持第一电阻改变层的电阻定律，尽管第一电阻改变层的侧面部分被蚀刻损坏。 电阻率存储器件包括第一电极（100），第一绝缘层，第一电阻改变层（120）和第一开关器件。 第一绝缘层装配在第一电极上。 第一绝缘层具有暴露第一电极的一部分的第一孔。 第一电阻改变层与暴露的第一电极接触。 第一电阻改变层在第一周围孔的第一绝缘层上扩展。 第一开关装置电连接到第一电阻改变层。
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公开(公告)号：KR1020090045653A
公开(公告)日：2009-05-08
申请号：KR1020070111584
申请日：2007-11-02
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: G11C11/36 , G11C11/14 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2013/009 , G11C2013/0092 , G11C2213/32 , G11C2213/71 , G11C2213/72 , G11C2213/73 , G11C2213/76 , H01L27/1021 , H01L21/28273
Abstract: 본 발명은 고밀도 비휘발성 메모리 소자를 구현하기 위하여 별도로 형성된 스위칭 소자가 필요없이 간단한 구조로 구동할 수 있는 다이오드 특성을 지닌 비휘발성 메모리 소자 및 이를 포함하는 메모리 어레이에 관한 것이다. 제 1전극; 상기 제1전극 상에 형성된 다이오드-스토리지 노드; 및 상기 다이오드-스토리지 노드 상에 형성된 제 2전극;을 포함하는 비휘발성 메모리 소자를 제공한다.
저항 변화 메모리, 다이오드, 비휘발성 메모리, 크로스 포인트-
公开(公告)号：KR1020080112609A
公开(公告)日：2008-12-26
申请号：KR1020070061207
申请日：2007-06-21
Applicant: 삼성전자주식회사
IPC: H01L27/115 , B82Y40/00
CPC classification number: G11C13/0004 , B82Y10/00
Abstract: A resistivity memory device and manufacturing method thereof are provided to control the location and form of an overhanging construction selectively and arbitrarily by providing various manufacturing methods of the overhanging construction formed in a middle electrode. A resistivity memory device comprises a middle electrode(32), a resistance conversion layer(33) and an upper electrode(34). The middle electrode is formed on a switch(31). The middle electrode is composed of a overhanging construction(p). The resistance conversion layer is formed on the middle electrode. The upper electrode is formed on the resistance conversion layer.
Abstract translation: 提供一种电阻率记忆装置及其制造方法，通过提供形成在中间电极中的突出结构的各种制造方法，有选择地和任意地控制悬垂结构的位置和形状。 电阻率存储器件包括中间电极（32），电阻转换层（33）和上电极（34）。 中间电极形成在开关（31）上。 中间电极由突出构造（p）组成。 电阻转换层形成在中间电极上。 上电极形成在电阻转换层上。
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公开(公告)号：KR101356696B1
公开(公告)日：2014-01-29
申请号：KR1020070082989
申请日：2007-08-17
Applicant: 삼성전자주식회사
IPC: H01L29/86 , H01L29/861
CPC classification number: H01L29/242 , H01L27/1021 , H01L27/24 , H01L29/24 , H01L29/267 , H01L29/8618
Abstract: 본 발명은 다이오드 구조체 및 이를 포함하는 메모리 소자에 관한 것이다. 다이오드 구조체에 있어서, 제 1전극 상기 제 1 전극 상에 형성된 p형 Cu 산화층 상기 p형 Cu 산화층 상에 형성된 n형 InZn 산화층 및 상기 n형 InZn 산화층 상에 형성된 제 2전극을 포함하는 다이오드 구조체 및 이를 포함하는 메모리 소자를 제공한다.
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