公开(公告)号：AT186412T

公开(公告)日：1999-11-15

申请号：AT94303783

申请日：1994-05-25

Applicant: IBM

Inventor： AMINI NADER ,  BLAND PATRICK MAURICE ,  BOURY BECHARA FOUAD ,  HOFMANN RICHARD GERARD ,  LOHMAN TERENCE JOSEPH

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/40

Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24 connected to system memory 32 by a first system bus 36, and a second system bus 16 connected to the CPU; (ii) a host bridge 20 connecting the second system bus to a peripheral bus 22; (iii) an input/output (I/O) bridge 78 connecting the peripheral bus to a standard I/O bus 92, the standard I/O bus having a plurality of standard I/O devices 90 attached thereto; and (v) arbitration logic 42 which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller 40 for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.

公开(公告)号：SG44431A1

公开(公告)日：1997-12-19

申请号：SG1996000365

申请日：1990-05-16

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  MILLING PHILIP E

IPC: G06F12/08

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：SG44402A1

公开(公告)日：1997-12-19

申请号：SG1996000189

申请日：1989-04-11

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD ,  GAUDENZI GENE JOSEPH ,  KRAMER KEVIN GERRARD ,  TEMPEST SUSAN LYNN

IPC: G06F11/10 ,  G06F13/38 ,  G06F13/40 ,  H03K3/288 ,  H03K19/082 ,  H03K3/356 ,  H03K3/037

Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes : a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data patch comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanism for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

公开(公告)号：PL320022A1

公开(公告)日：1997-09-01

申请号：PL32002295

申请日：1995-11-27

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  CRONIN DANIEL RAYMOND ,  HOFMANN RICHARD GERARD ,  MOELLER DENNIS ,  VENARCHICK LANCE MICHAEL

IPC: G06F12/06 ,  G06F13/28 ,  G06F13/36 ,  G06F13/40

Abstract: A computer system that has two buses (30, 32) with different memory addressing capacities and a first bus master (36) that generates M-bit addresses is provided with a bridge (34) between the two buses. In order to generate N-bit addresses for use on the second bus (30), a direct memory access (DMA) controller (50) on the bridge produces P bits, where P + M = N. The P bits are concentrated with the M bits to form an N-bit address used on the second bus (30) to address memory (40). The addition of P bits reallocates the memory segment addressable by the M-bits to any location within the memory map addressable by an N-bit address.

公开(公告)号：FI96244C

公开(公告)日：1996-05-27

申请号：FI891788

申请日：1989-04-14

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08

公开(公告)号：CA1338155C

公开(公告)日：1996-03-12

申请号：CA596778

申请日：1989-04-14

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD ,  GAUDENZI GENE JOSEPH ,  KRAMER KEVIN GERRARD ,  TEMPEST SUSAN LYNN

IPC: G06F11/10 ,  G06F13/38 ,  G06F13/40 ,  H03K3/288 ,  H03K19/082 ,  H04L5/14

Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

公开(公告)号：DE68923402T2

公开(公告)日：1996-03-07

申请号：DE68923402

申请日：1989-03-03

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08

Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.

公开(公告)号：HK23896A

公开(公告)日：1996-02-16

申请号：HK23896

申请日：1996-02-08

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F13/36 ,  G06F13/362 ,  G11C11/401 ,  G11C7/10 ,  G11C7/00

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.

公开(公告)号：HK23696A

公开(公告)日：1996-02-16

申请号：HK23696

申请日：1996-02-08

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/44 ,  G06F9/445 ,  G06F13/36 ,  G06F13/362

Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

公开(公告)号：ES2075856T3

公开(公告)日：1995-10-16

申请号：ES89480053

申请日：1989-04-11

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  KRAMER KEVIN GERRARD ,  DEAN MARK EDWARD ,  TEMPEST SUSAN LYNN ,  GAUDENZI GENE JOSEPH

IPC: G06F11/10 ,  G06F13/38 ,  G06F13/40 ,  H03K3/288 ,  H03K19/082 ,  H03K19/00 ,  H03K19/0175

Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes : a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data patch comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanism for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.