公开(公告)号：DE112004000464T5

公开(公告)日：2006-06-01

申请号：DE112004000464

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

公开(公告)号：GB2413876A

公开(公告)日：2005-11-09

申请号：GB0516192

申请日：2004-05-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY JOHN ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

Abstract: Selected units of storage, such as segments of storage or regions of storage, are invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additionally, buffer entries associated with the invalidated units of storage or other chosen units of storage are cleared. An instruction is provided to perform the invalidation and/or clearing. Moreover, buffer entries associated with a particular address space are cleared, without any invalidation. This is also performed by the instruction. The instruction can be implemented in software, hardware, firmware or some combination thereof, or it can be emulated.

公开(公告)号：BR112023021648A2

公开(公告)日：2023-12-26

申请号：BR112023021648

申请日：2022-05-31

Applicant: IBM

Inventor： GIAMEI BRUCE ,  BORNTRAEGER CHRISTIAN ,  YOST CHRISTINE ,  OSISEK DAMIAN ,  TZORTZATOS ELPIDA ,  HELLER LISA ,  SLEGEL TIMOTHY ,  GAERTNER UTE

IPC: G06F12/14 ,  G06F12/1009 ,  G06F12/1027

Abstract: instrução de redefinição de proteção de tradução de endereço dinâmico. uma instrução é fornecida para executar uma operação de redefinição de proteção de tradução de endereço quando executada. a execução da instrução inclui determinar, por um processador, que um bit de proteção de tradução de endereço em uma entrada de tabela de tradução especificada associada a um bloco de armazenamento deve ser redefinido. com base na determinação de que o bit de proteção de tradução de endereço deve ser redefinido, a execução da instrução inclui a redefinição do bit de proteção de tradução de endereço para desativar a proteção contra gravação para o bloco de armazenamento. a redefinição está ausente, aguardando uma ação de um ou mais outros processadores do ambiente de computação.

公开(公告)号：AU2020237597B2

公开(公告)日：2022-11-24

申请号：AU2020237597

申请日：2020-02-28

Applicant: IBM

Inventor： BORNTRAEGER CHRISTIAN ,  IMBRENDA CLAUDIO ,  BUSABA FADI ,  BRADBURY JONATHAN ,  HELLER LISA

IPC: G06F21/12 ,  G06F9/455 ,  G06F21/51 ,  G06F21/53 ,  G06F21/57 ,  G06F21/62 ,  G06F21/74

Abstract: A method is provided by a secure interface control of a computer that provides a partial instruction interpretation for an instruction which enables an interruption. The secure interface control fetches a program status word or a control register value from a secure guest storage. The secure interface control notifies an untrusted entity of guest interruption mask updates. The untrusted entity is executed on and in communication with hardware of the computer through the secure interface control to support operations of a secure entity executing on the untrusted entity. The secure interface control receives, from the untrusted entity, a request to present a highest priority, enabled guest interruption in response to the notifying of the guest interruption mask updates. The secure interface control moves interruption information into a guest prefix page and injecting the interruption in the secure entity when an injection of the interruption is determined to be valid.

公开(公告)号：DE112020000303T5

公开(公告)日：2021-09-30

申请号：DE112020000303

申请日：2020-03-06

Applicant: IBM

Inventor： HELLER LISA ,  BASUBA FADI

IPC: G06F21/53

Abstract: Ein Verfahren zum Testen von Speicherschutz-Hardware umfasst ein Empfangen, von einer nicht vertrauenswürdigen Entität, die auf einem Host-Server ausgeführt wird, einer Anforderung zum Zuteilen einer sicheren Entität. Durch eine sichere Schnittstellensteuerung des Host-Servers wird bestimmt, ob sich der Host-Server in einem sicheren Hilfs- (AS) Debug-Modus zum Testen einer AS-Entität befindet. Auf Grundlage des Bestimmens, dass sich der Host-Server in dem AS-Debug-Modus befindet, wird ein sicherer Gast-Entitätszustand aus einem Zustandsdeskriptor für die sichere Entität in einen AS-Entitätszustand in Hardware geladen, um nach Zuteilung der sicheren Entität Zugriffe auf Seiten in einem Arbeitsspeicher zu testen, die als „Sicher“ und als der AS-Entität zugehörig registriert sind.

公开(公告)号：SG11202105425TA

公开(公告)日：2021-06-29

申请号：SG11202105425T

申请日：2020-03-06

Applicant: IBM

Inventor： IMBRENDA CLAUDIO ,  BORNTRAEGER CHRISTIAN ,  HELLER LISA ,  BUSABA FADI ,  BRADBURY JONATHAN

IPC: G06F21/62 ,  G06F9/455 ,  G06F12/10

Abstract: According to one or more embodiments of the present invention, a computer implemented method includes receiving, at a secure interface control of a computer system, an access request for a data structure related to a secure entity in a secure domain of the computer system. The secure interface control can check for a virtual storage address associated with a location of the data structure. The secure interface control can request an address translation using a virtual address space of a non-secure entity of the computer system based on determining that the location of the data structure is associated with the virtual storage address. The secure interface control can access the data structure based on a result of the address translation.

公开(公告)号：SG11202105420VA

公开(公告)日：2021-06-29

申请号：SG11202105420V

申请日：2020-03-06

Applicant: IBM

Inventor： HELLER LISA ,  BUSABA FADI ,  BRADBURY JONATHAN

IPC: G06F12/14

Abstract: A method is provided. A secure interface control in communication with an untrusted entity perform the method. In this regard, the secure interface control implements an initialization instruction to set donated storage as secure. The implementing of the initialization instruction is responsive to an instruction call issued from the untrusted entity.

公开(公告)号：AU2020233905A1

公开(公告)日：2021-06-10

申请号：AU2020233905

申请日：2020-02-26

Applicant: IBM

Inventor： HELLER LISA ,  BUSABA FADI ,  BRADBURY JONATHAN ,  BORNTRAEGER CHRISTIAN ,  BACHER UTZ ,  BUENDGEN REINHARD

IPC: G06F21/74 ,  G06F9/30

Abstract: A method is provided. The method is implemented by a communication interface of a secure interface control executing between the secure interface control of a computer and hardware of the computer/ In this regard, the communication interface receives an instruction and determines whether the instruction is a millicoded instruction. Further, the communication interface enters a millimode comprising enabling the secure interface control to engage millicode of the hardware through the communication interface based on the instruction being the millicoded instruction. The millicode, then, executes the instruction

公开(公告)号：AU2015330266B2

公开(公告)日：2018-10-04

申请号：AU2015330266

申请日：2015-09-14

Applicant: IBM

Inventor： GAINEY CHARLES ,  FARRELL MARK ,  HELLER LISA ,  KUBALA JEFFREY PAUL ,  SCHMIDT DONALD WILLIAM ,  GREINER DAN ,  SLEGEL TIMOTHY ,  BUSABA FADI YUSUF ,  OSISEK DAMIAN ,  BRADBURY JONATHAN DAVID ,  LEHNERT FRANK ,  NERZ BERND ,  JACOBI CHRISTIAN

IPC: G06F9/455 ,  G06F9/48

Abstract: A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.

公开(公告)号：CA2708939C

公开(公告)日：2016-07-19

申请号：CA2708939

申请日：2009-02-16

Applicant: IBM

Inventor： SZWED PETER KENNETH ,  OSISEK DAMIAN ,  HELLER LISA ,  FARRELL MARK ,  GAINEY CHARLES JR ,  GREINER DAN

IPC: G06F11/07

Abstract: Management of storage used by pageable guests of a computing environment is facilitated. An enhanced suppression-on-protection facility is provided that enables the determination of which level of protection (host or guest) caused a fault condition, in response to an attempted storage access.