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公开(公告)号：DE69515991T2
公开(公告)日：2000-11-16
申请号：DE69515991
申请日：1995-05-19
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
IPC: G11C11/417 , G11C7/10 , H03K17/687 , H03K19/0175 , H03K19/0948 , G11C7/00 , G11C11/409
Abstract: An output stage for integrated circuits, particularly for electronic memories, comprising: an input section that is adapted to acquire an input datum; a latch circuit having a first output and a second output and connected to the input section; a first inverter connected to the second output; a second inverter connected to the first output; a third inverter connected to the output of the second inverter; a grounding transistor driven by the second output of the latch circuit and adapted to connect the output of the third inverter to the ground; and a push-pull stage driven by the output of the first and third inverters. The stage according to the present invention furthermore comprises: a shorting transistor adapted to connect the output of the first inverter to the output of the second inverter; a first enabling transistor interposed between the first inverter and the first output of the latch circuit; a second enabling transistor interposed between the second inverter and the second output of the latch circuit; and a section for charging and discharging the push-pull stage, which is adapted to rapidly discharge the gate of the first transistor of the push-pull stage and to charge the gate of the second transistor of the push-pull stage during their operation.
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公开(公告)号：DE69424764T2
公开(公告)日：2000-11-16
申请号：DE69424764
申请日：1994-01-28
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , MACCARRONE MARCO , PADOAN SILVIA
Abstract: A charge pump circuit (1) including a number of pull-up stages (2) connected in parallel with one another between a reference potential line (3) and an output line (4). Each stage (2) includes a capacitor (5) having a first terminal connected to a charging and discharging node (7), and a second terminal connected to a pull-up node (6) for switching between a first charging operating phase and a second charge transferring operating phase. The charging and discharging node (7) is connected to the supply line (3) via a charging transistor (9) having a control terminal connected to a high-voltage bias node (11) formed by the adjacent stage in the opposite operating phase, for charging the capacitor (5) substantially up to the supply voltage.
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公开(公告)号：DE69424860T2
公开(公告)日：2000-11-09
申请号：DE69424860
申请日：1994-02-18
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA
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公开(公告)号：DE69518632D1
公开(公告)日：2000-10-05
申请号：DE69518632
申请日：1995-06-26
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
IPC: G11C11/413 , G11C8/10 , G11C8/00
Abstract: A bit line selection decoder, particularly for electronic memories, comprising at least two bit lines, each of which can be selected by a respective switch, and a plurality of control lines that drive the switches. Its particularity resides in the fact that it comprises a decoder, in which the outputs drive the switches, and at least one first and one second bus of control lines that are arranged in input to the decoder and are adapted to address any one of the at least two bit lines.
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公开(公告)号：DE69424764D1
公开(公告)日：2000-07-06
申请号：DE69424764
申请日：1994-01-28
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , MACCARRONE MARCO , PADOAN SILVIA
Abstract: A charge pump circuit (1) including a number of pull-up stages (2) connected in parallel with one another between a reference potential line (3) and an output line (4). Each stage (2) includes a capacitor (5) having a first terminal connected to a charging and discharging node (7), and a second terminal connected to a pull-up node (6) for switching between a first charging operating phase and a second charge transferring operating phase. The charging and discharging node (7) is connected to the supply line (3) via a charging transistor (9) having a control terminal connected to a high-voltage bias node (11) formed by the adjacent stage in the opposite operating phase, for charging the capacitor (5) substantially up to the supply voltage.
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Patent Agency Ranking
公开(公告)号：ITTO980840A1
公开(公告)日：2000-04-06
申请号：ITTO980840
申请日：1998-10-06
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
IPC: G11C8/18
Abstract: An address transition detector in a semiconductor memories, which provides means for obtaining two complementary address transition signals from an address signal and send them to a monostable circuit apt to emit output pulse signals on an output node as a function of logical status changements of said address signal, said monostable circuit comprising bistable memory circuits for storing the values of the address transition signals at each logical status changement of the adddress signal through a feedback path, said values of the address transition signals being apt to control selection means of the complementary address transition signals. According to the present invention, said monostable circuit (123; 223; 303; 403) has breaking means (140; 240; 340; 440) of the feedback path (FB) in response to an enable signal (AE).
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公开(公告)号：DE69514793D1
公开(公告)日：2000-03-02
申请号：DE69514793
申请日：1995-08-03
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
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公开(公告)号：DE69326154T2
公开(公告)日：2000-02-24
申请号：DE69326154
申请日：1993-11-30
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , PADOAN SILVIA
Abstract: An integrated circuit for the programming of a memory cell in a non-volatile memory register, said memory cell comprising at least one programmable non-volatile memory element (TF;TF0,TF1) having a cotrol electrode and a supply electrode and being suitable to store one bit of information and a load circuit (LC;T0-T3) associated to said memory element (TF;TF0,TF1) to read the information stored therein, comprises switching means (TS;T4,T5), connected in series between the supply electrode of said at least one memory element (TF;TF0,TF1) and a respective data line (A;A,AN) carrying a datum to be programmed into said memory element (TF;TF0,TF1); the switching means are controlled by a signal (7) which determines the switching means (TS;T4,T5) to electrically connect the memory element (TF;TF0,TF1) to the data line (A;A,AN) when the memory cell of the non-volatile memory register is to be programmed.
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公开(公告)号：ITMI992465D0
公开(公告)日：1999-11-25
申请号：ITMI992465
申请日：1999-11-25
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
IPC: G11C8/10
Abstract: A decoder with reduced complexity includes at least one OR circuit section and at least one AND circuit section. The at least one OR circuit section may include first and second circuit lines mutually connected and respectively receiving as inputs an address signal and an inverted address signal. The at least one AND circuit section may include first and second circuit lines which respectively receive as inputs the inverted address signal and the address signal. The at least one OR circuit section and the at least one AND circuit section may be connected to first and second booster circuits. Furthermore, the at least one OR circuit section may also include a virtual ground.
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公开(公告)号：DE69419403D1
公开(公告)日：1999-08-12
申请号：DE69419403
申请日：1994-02-18
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , MACCARRONE MARCO , OLIVO MARCO
Abstract: A load timing circuit (20) including an out-like circuit (21) identical to the output circuits of the memory, so as to present the same propagation time; a simulating signal source (34) for generating a data simulating signal (SP); a synchronizing network (30, 32) for detecting a predetermined switching edge of the data simulating signal (SP) and enabling (35) supply of the signal to the out-like circuit (21) and data supply to the output circuits of the memory; a combinatorial network (29, 30) for detecting propagation of the data simulating signal (SP) to the output of the out-like circuit and disabling the data simulating signal (SP); and a reset element (33) for resetting the timing circuit (20).
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