中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

38 records (took 0.021 seconds)

    CHARGE PUMP CIRCUIT
    2.
    发明专利
    CHARGE PUMP CIRCUIT 失效

    公开(公告)号：JPH0847246A

    公开(公告)日：1996-02-16

    申请号：JP1306395

    申请日：1995-01-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  MACCARRONE MARCO ,  PADOAN SILVIA

    IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  H02M3/07

    Abstract: PURPOSE: To supply large power in the case that an input/output voltage ratio is low or a power supply voltage is low by mutually connecting in parallel pull-up stages between a reference potential line and an output line. CONSTITUTION: This charge pump circuit 1 is provided with numerous stages 21 -2n connected in parallel to each other between the reference potential line 3 and the output line 4, the respective stages 21 -2n are provided with bootstrap capacitors 51 -5n , the one side is connected to nodes 71 -7n and the other terminals are connected to nodes 61 -6n . Then, when inverters 121 -12n are switched, the odd-numbered stages 21 , 23 ,... are switched to a charge transfer mode, the even- numbered stages are switched to a charging mode. When a switching edge reaches a stage 2n-1 which is one next to the last, an AND circuit 15 and a NOR circuit 16 are switched, shifting along the inverters 121 -12n is performed, the odd-numbered stages 21 , 23 ,... are charged, and the even-numbered stages 22 , 24 ,... transfer the stored charges. As a result, even in the case that an input voltage ratio is low, voltage is efficiently boosted and a large power is supplied.

    REGULATING CIRCUIT AND DISCHARGE CONTROL METHOD THEREOF
    3.
    发明专利
    REGULATING CIRCUIT AND DISCHARGE CONTROL METHOD THEREOF 失效

    公开(公告)号：JPH07326195A

    公开(公告)日：1995-12-12

    申请号：JP5656995

    申请日：1995-02-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOLLA CARLA ,  PADOAN SILVIA ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/14 ,  G11C16/16

    Abstract: PURPOSE: To prevent the occurrence of erase and change of contents of non- specified memory cells by providing a normally-open switch and a current generator to control a discharge current. CONSTITUTION: A memory cell 5 to be erased is specified. For performing the erasing, a programming voltage Vpp from a logical switch SW is connected to the cell to set a source line SRC a high voltage a normally-open switch 11 of control transistors M2 and M3 and an erase transistor M4. After completion of the erase stage, the line SRC has an erase voltage value higher than the high potential, which voltage is discharged to the ground. This causes a signal SL to be set at its high level, thus turning a switch I1 ON. This causes the voltage of the line SRC to be controlled by a current IS to continue slow discharging operation. In this way, since the discharging operation of the source line SRC is controlled to be gradually slow, the occurrence of erase/change of contents of the memory cells 5 other than the specified cell can be prevented.

    CIRCUIT DEVICE FOR MEASURING DISTRIBUTION OF THRESHOLD VOLTAGE IN NONVOLATILE MEMORY-CELL
    4.
    发明专利
    CIRCUIT DEVICE FOR MEASURING DISTRIBUTION OF THRESHOLD VOLTAGE IN NONVOLATILE MEMORY-CELL 失效

    公开(公告)号：JPH07272500A

    公开(公告)日：1995-10-20

    申请号：JP7186195

    申请日：1995-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PADOAN SILVIA ,  MACCARRONE MARCO ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56 ,  G11C16/06

    Abstract: PURPOSE: To improve and facilitate the measurement of the distribution of threshold voltage in a non-volatile memory-cell further. CONSTITUTION: A circuit device 1 for measuring the distribution of threshold voltage has a differential amplifier 3 connected to a circuit leg containing a memory-cell 2 and a reference circuit leg 4 and a circuit means unbalancing the values of currents flowing through each circuit leg. The circuit means comprises a variable current generator related to the reference circuit leg 4, the variable current generator is connected between a supply-voltage Vdd reference point and a ground-voltage GND reference point, and a current I2 as the function of supply voltage Vdd is generated in the reference circuit leg 4.

    STANDARD POTENTIAL GENERATION CIRCUIT
    5.
    发明专利
    STANDARD POTENTIAL GENERATION CIRCUIT 失效

    公开(公告)号：JPH07235642A

    公开(公告)日：1995-09-05

    申请号：JP29764694

    申请日：1994-11-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PADOAN SILVIA ,  GOLLA CARLA

    IPC: H01L27/04 ,  G05F3/24 ,  H01L21/822

    Abstract: PURPOSE: To provide a circuit configuration which can supply, with a highly simple arrangement, an accurate and stable reference potential and at the same time, can stabilize the power supply, even when temperature and process parameters vary. CONSTITUTION: This circuit includes at least one field effect transistor (M1) 103 and a resistive bias element (R) 102, connected in series with a supply power VCC between the supply power and ground, and a second field effect transistor (M2) 104 connected to the transistor 103 in such a manner that a reference potential can be extracted as a difference between the threshold voltages of the 2 transistors.

    READ TIMING METHOD OF NONVOLATILE MEMORY AND CIRCUIT
    7.
    发明专利
    READ TIMING METHOD OF NONVOLATILE MEMORY AND CIRCUIT 失效

    公开(公告)号：JPH0855485A

    公开(公告)日：1996-02-27

    申请号：JP4796295

    申请日：1995-02-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

    Abstract: PURPOSE: To derive optimum performance from a memory by enabling the circuit with a switching edge, making the circuit programmable, and protecting the circuit against noise. CONSTITUTION: A delay unit 23 inputs a low-level signal, which goes up to a high level a delay time corresponding to the contents of memory elements 20 and 22 after a leading edge of a signal ATD is received, to a NOR gate 27. The gate 27 inputs a signal PC as a signal DET to an asymmetrical delay unit 24 through a NOR gate 28, and a low-level data simulation signal SP is outputted which goes up to the high level a delay time based upon the elements 20 and 21 after a leading edge of the signal DET is received. The signal SP is transferred to an output similar circuit 33 and at its completion time, a high level is outputted. Consequently, signals N and L are switched to the low level and the output STP of a continuance expanding circuit 51 goes down to a low level. Consequently, the data loading is completed. This loading lasts accurately in an output circuit 108 during data propagation.

    READ DEVICE OF MEMORY ARRAY CELL
    8.
    发明专利
    READ DEVICE OF MEMORY ARRAY CELL 失效

    公开(公告)号：JPH0836884A

    公开(公告)日：1996-02-06

    申请号：JP6279395

    申请日：1995-03-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOLLA CARLA MARIA ,  OLIVO MARCO ,  PADOAN SILVIA

    IPC: G11C11/409 ,  G11C7/00 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28

    Abstract: PURPOSE: To provide equal current paths with a compact structure, and exhibit the possibility of switching one or more current paths. CONSTITUTION: A current path of an array branch 21 is constituted of a load transistor 27, and current paths 32a, 33a of a reference branch 22 are constituted of load transistors 32, 33. The load transistor 32 is connected with a diode, and the load transistor 33 is switchable by a switching network (35-50) connected to a gate terminal of the load transistor 33.

    VOLTAGE REGULATOR, ITS PROGRAMMING-VOLTAGE SUPPLY METHOD, AND BIAS-CURRENT CORRECTION METHOD AND MEMORY DEVICE
    9.
    发明专利
    VOLTAGE REGULATOR, ITS PROGRAMMING-VOLTAGE SUPPLY METHOD, AND BIAS-CURRENT CORRECTION METHOD AND MEMORY DEVICE 失效

    公开(公告)号：JPH07235194A

    公开(公告)日：1995-09-05

    申请号：JP11995

    申请日：1995-01-04

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MACCARRONE MARCO ,  OLIVO MARCO ,  GOLLA CARLA ,  PADOAN SILVIA

    IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

    Abstract: PURPOSE: To improve both stability and reliability by using a current mirror, a resistive divider, an amplifier stage, a source follow-up transistor TR and a resistive path connected to a reference potential. CONSTITUTION: A current mirror 3 corrects the voltage drop that is caused by the serial resistance of a bit line where its programming is ready. Then this programming is carried out by giving the voltage which varies according to the current draw of one or plural cells to be programmed to the reference potential that is obtained from reference voltage VPP via a resistive divider 2. A TR MG2 is prepared to hold a resistive path 8 reaching the ground from the programming voltage VP, and the bias current is partly subtracted from an inverted current. This subtraction part is decided by the W/L ratio of a TR contained in the mirror 3. As a result, any offset voltage that is generated on a programming line can be corrected.

Patent Agency Ranking